DM504 datasheet(101/211 Pages) TI1

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DM504

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SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017

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Specifications

Table 5-32. VIN2 IOSETs (continued)

SIGNALS

IOSET1

IOSET2

IOSET3

BALL

MUX

BALL

MUX

BALL

MUX

vin2a_d14

vin2a_d15

5.9.6.3

DSS

Display Parallel Interfaces (DPI) channels are available in DSS named DPI Video Output 1.

Every VOUT interface consists of:

•

24-bit data bus (data[23:0])

•

Horizontal synchronization signal (HSYNC)

•

Vertical synchronization signal (VSYNC)

•

Data enable (DE)

•

Field ID (FID)

•

Pixel clock (CLK)

NOTE

For more information, see the Display Subsystem chapter of the Device TRM.

CAUTION

All pads/balls configured as vouti_* signals must be programmed to use slow

slew rate by setting the corresponding CTRL_CORE_PAD_*[SLEWCONTROL]

Table 5-33 and Figure 5-15 assume testing over the recommended operating conditions and electrical

characteristic conditions.

Table 5-33. DPI Video Output 1 Switching Characteristics(1)(2)

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

tc(clk)

Cycle time, output pixel clock vouti_clk

6.73

tw(clkL)

Pulse duration, output pixel clock vouti_clk low

P*0.5-1

tw(clkH)

Pulse duration, output pixel clock vouti_clk high

P*0.5-1

td(clk-ctlV)

Delay time, output pixel clock vouti_clk transition to output

data vouti_d[23:0] valid

DPI1

-1.33

1.01

td(clk-dV)

Delay time, output pixel clock vouti_clk transition to output

control signals vouti_vsync, vouti_hsync, vouti_de, and

vouti_fld valid

DPI1

-1.33

1.01

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