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DM504 Datasheet(PDF) 104 Page - Texas Instruments

Part # DM504
Description  SoC for Vision Analytics 12mm Package (ABE) Silicon Revision 2.0
PDF  211 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DM504 Datasheet(HTML) 104 Page - Texas Instruments

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104
DM504
SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017
www.ti.com
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Specifications
Copyright © 2016–2017, Texas Instruments Incorporated
For more information, please contact your local TI representative.
5.9.6.5
EMIF
The device has a dedicated interface to LPDDR2 SDRAM. It supports JEDEC standard compliant
LPDDR2 SDRAM devices with the following features:
•
16-bit or 32-bit data path to external SDRAM memory
•
Memory device capacity: 128Mb, 256Mb, 512Mb, 1Gb, 2Gb, 4Gb and 8Gb devices (Single die only)
•
One interface with associated LPDDR2 PHYs
NOTE
For more information, see the EMIF Controller section of the Device TRM.
5.9.6.6
GP Timers
The device has eight GP timers: TIMER1 through TIMER8.
•
TIMER1 (1-ms tick) includes a specific function to generate accurate tick interrupts to the operating
system and it belongs to the PD_WKUPAON domain.
•
TIMER2 through TIMER8 belong to the PD_COREAON module.
Each timer can be clocked from the system clock (19.2, 20, or 27 MHz) or the 32-kHz clock. Select the
clock source at the power, reset, and clock management (PRCM) module level.
Each timer provides an interrupt through the device IRQ_CROSSBAR.
Each timer is connected to an external pin by their PWM output or their event capture input pin (for
external timer triggering).
5.9.6.6.1 GP Timer Features
The following are the main features of the GP timer controllers:
•
Level 4 (L4) slave interface support:
–
32-bit data bus width
–
32- or 16-bit access supported
–
8-bit access not supported
–
10-bit address bus width
–
Burst mode not supported
–
Write nonposted transaction mode supported
•
Interrupts generated on overflow, compare, and capture
•
Free-running 32-bit upward counter
•
Compare and capture modes
•
Autoreload mode
•
Start and stop mode
•
Programmable divider clock source (2n, where n = [0:8])
•
Dedicated input trigger for capture mode and dedicated output trigger/PWM signal
•
Dedicated GP output signal for using the TIMERi_GPO_CFG signal
•
On-the-fly read/write register (while counting)
•
1-ms tick with 32.768-Hz functional clock generated (only TIMER1)



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