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DM504 Datasheet(PDF) 106 Page - Texas Instruments |
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DM504 Datasheet(HTML) 106 Page - Texas Instruments |
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106 / 211 page  10 8 4 3 7 12 5 6 14 2 3 13 Stop Start Repeated Start Stop I2Ci_SDA I2Ci_SCL 1 11 9 SPRS91v_I2C_01 106 DM504 SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017 www.ti.com Submit Documentation Feedback Specifications Copyright © 2016–2017, Texas Instruments Incorporated (4) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal. (5) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. Figure 5-16. I2C Receive Timing Table 5-36 and Figure 5-17 assumes testing over the recommended operating conditions and electrical characteristic conditions below. Table 5-36. Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings(2) NO. PARAMETER DESCRIPTION STANDARD MODE FAST MODE UNIT MIN MAX MIN MAX 16 tc(SCL) Cycle time, SCL 10 2.5 µs 17 tsu(SCLH-SDAL) Setup time, SCL high before SDA low (for a repeated START condition) 4.7 0.6 µs 18 th(SDAL-SCLL) Hold time, SCL low after SDA low (for a START and a repeated START condition) 4 0.6 µs 19 tw(SCLL) Pulse duration, SCL low 4.7 1.3 µs 20 tw(SCLH) Pulse duration, SCL high 4 0.6 µs 21 tsu(SDAV-SCLH) Setup time, SDA valid before SCL high 250 100 ns 22 th(SCLL-SDAV) Hold time, SDA valid after SCL low (for I2C bus devices) 0 3.45 0 0.9 µs 23 tw(SDAH) Pulse duration, SDA high between STOP and START conditions 4.7 1.3 µs 24 tr(SDA) Rise time, SDA 1000 20 + 0.1Cb (1) 300 ns 25 tr(SCL) Rise time, SCL 1000 20 + 0.1Cb (1) 300 ns 26 tf(SDA) Fall time, SDA 300 20 + 0.1Cb (1) 300 ns 27 tf(SCL) Fall time, SCL 300 20 + 0.1Cb (1) 300 ns 28 tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) 4 0.6 µs 29 Cp Capacitance for each I2C pin 10 10 pF |
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