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DM504 Datasheet(PDF) 105 Page - Texas Instruments |
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DM504 Datasheet(HTML) 105 Page - Texas Instruments |
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105 / 211 page  105 DM504 www.ti.com SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017 Submit Documentation Feedback Specifications Copyright © 2016–2017, Texas Instruments Incorporated 5.9.6.7 I2C The device includes 2 inter-integrated circuit (I2C) modules which provide an interface to other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1. External components attached to this 2-wire serial bus can transmit/receive 8-bit data to/from the device through the I2C module. NOTE Note that, I2C1 and I2C2, due to characteristics of the open drain IO cells, HS mode is not supported. NOTE Inter-integrated circuit i (i=1 to 2) module is also referred to as I2Ci. NOTE For more information, see the Multimaster I2C Controller section of the Device TRM. Table 5-35 and Figure 5-16 assumes testing over the recommended operating conditions and electrical characteristic conditions below. Table 5-35. Timing Requirements for I2C Input Timings(1) NO. PARAMETER DESCRIPTION STANDARD MODE FAST MODE UNIT MIN MAX MIN MAX 1 tc(SCL) Cycle time, SCL 10 2.5 µs 2 tsu(SCLH-SDAL) Setup time, SCL high before SDA low (for a repeated START condition) 4.7 0.6 µs 3 th(SDAL-SCLL) Hold time, SCL low after SDA low (for a START and a repeated START condition) 4 0.6 µs 4 tw(SCLL) Pulse duration, SCL low 4.7 1.3 µs 5 tw(SCLH) Pulse duration, SCL high 4 0.6 µs 6 tsu(SDAV-SCLH) Setup time, SDA valid before SCL high 250 100(2) ns 7 th(SCLL-SDAV) Hold time, SDA valid after SCL low 0(3) 3.45(4) 0(3) 0.9(4) µs 8 tw(SDAH) Pulse duration, SDA high between STOP and START conditions 4.7 1.3 µs 9 tr(SDA) Rise time, SDA 1000 20 + 0.1Cb (5) 300 ns 10 tr(SCL) Rise time, SCL 1000 20 + 0.1Cb (5) 300 ns 11 tf(SDA) Fall time, SDA 300 20 + 0.1Cb (5) 300 ns 12 tf(SCL) Fall time, SCL 300 20 + 0.1Cb (5) 300 ns 13 tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) 4 0.6 µs 14 tw(SP) Pulse duration, spike (must be suppressed) 0 50 ns 15 Cb (5) Capacitive load for each bus line 400 400 pF (1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down. (2) A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns (according to the Standard-mode I2C-Bus Specification) before the SCL line is released. (3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. |
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