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DM504 Datasheet(PDF) 140 Page - Texas Instruments |
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DM504 Datasheet(HTML) 140 Page - Texas Instruments |
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140 / 211 page  jtag_tck jtag_tms_tmsc(IN) jtag_tms_tmsc(OUT) CJ2 CJ9a CJ9b CJ1 CJ1b CJ1a SPRS91v_JTAG_03 CJ10a CJ10b CJ11 CJ13 140 DM504 SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017 www.ti.com Submit Documentation Feedback Specifications Copyright © 2016–2017, Texas Instruments Incorporated 5.9.7.2 Compact JTAG Interface (cJTAG) The cJTAG module is a component which can run a 2-pin communication protocol on top of an IEEE 1149.1 JTAG Test Access Port (TAP). The cJTAG logic serializes the IEEE 1149.1 transactions, using a variety of compression formats, to reduce the number of pins needed to implement a JTAG debug and boundary scan port. Table 5-76, Table 5-77 and Figure 5-43 assume testing over the recommended operating conditions and electrical characteristic conditions below. Table 5-76. Timing Requirements for IEEE 1149.7 cJTAG NO. PARAMETER DESCRIPTION MIN MAX UNIT CJ1 tc(TCK) Cycle time, TCK 62.29 ns CJ1a tw(TCKH) Pulse duration, TCK high (40% of tc) 24.92 ns CJ1b tw(TCKL) Pulse duration, TCK low(40% of tc) 24.92 ns CJ9a tsu(TMSC-TCKre) Input setup time, TMSC valid to TCK high (RE timing selected) 12.46 ns CJ10a tsu(TMSC-TCKfe) Input setup time, TMSC valid to TCK low (FE timing selected) 12.46 ns CJ9b th(TCKre-TMSC) Input hold time, TMSC valid from TCK high (RE timing selected) 0.00 ns CJ10b th(TCKfe-TMSC) Input hold time, TMSC valid from TCK low (FE timing selected) 0.00 ns Table 5-77. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.7 cJTAG NO. PARAMETER DESCRIPTION MIN MAX UNIT CJ11 td(TCKL-TMSCV) Delay time, TCK low to TMSC valid 0 12.45 ns CJ13 td(TCKH-TMSCZ) Delay time, TCK high to TMSC HiZ 0 20.7 ns CJ12 td(TMSCV-KPRV) Delay time, TMSC valid to Keeper Valid 0 18 ns CJ2 td(TCKL-TDOV) Delay time, TCK low to TDO valid 0 29.14 ns Figure 5-43. cJTAG Interface Timing—Normal Mode 5.9.7.3 Trace Port Interface Unit (TPIU) 5.9.7.3.1 TPIU PLL DDR Mode Table 5-78 and Figure 5-44 assume testing over the recommended operating conditions and electrical characteristic conditions below. Table 5-78. Switching Characteristics for TPIU NO. PARAMETER DESCRIPTION MIN MAX UNIT TPIU1 tc(clk) Cycle time, TRACECLK period 5.56 ns TPIU4 td(clk-ctlV) Skew time, TRACECLK transition to TRACECTL transition -1.61 1.98 ns TPIU5 td(clk-dataV) Skew time, TRACECLK transition to TRACEDATA[17:0] transition -1.61 1.98 ns |
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