DM504 datasheet(144/211 Pages) TI1

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DM504

SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017

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Detailed Description

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A TMS320C66x™ CorePac DSP core that encompasses:

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L1 program-dedicated (L1P) cacheable memory

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L1 data-dedicated (L1D) cacheable memory

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L2 (program and data) cacheable memory

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Extended Memory Controller (XMC)

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External Memory Controller (EMC)

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DSP CorePac located interrupt controller (INTC)

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DSP CorePac located power-down controller (PDC)

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Dedicated enhanced data memory access engine - EDMA, to transfer data from/to memories and

peripherals external to the DSP subsystem and to local DSP memory (most commonly L2 SRAM). The

external DMA requests are passed through DSP system level (SYS) wakeup logic, and collected from

the DSP1 dedicated output of the device DMA Events Crossbar for the subsystem.

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A level 2 (L2) interconnect network (DSP NoC) to allow connectivity between different modules of the

subsystem or the remainder of the device via the device L3_MAIN interconnect.

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Two memory management units (on EDMA L2 interconnect and DSP MDMA paths) for accessing the

device L3_MAIN interconnect address space.

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Dedicated system control logic (DSP_SYSTEM) responsible for power management, clock generation,

and connection to the device power, reset, and clock management (PRCM) module

The TMS320C66x Instruction Set Architecture (ISA) is the latest for the C6000 family. As with its

predecessors (C64x, C64x+ and C674x), the C66x is an advanced VLIW architecture with 8 functional

units (two multiplier units and six arithmetic logic units) that operate in parallel. The C66x CPU has a total

of 64 general-purpose 32-bit registers.

Some features of the DSP C6000 family devices are:

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Advanced VLIW CPU with eight functional units (two multipliers and six ALUs) which:

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Executes up to eight instructions per cycle for up to ten times the performance of typical DSPs

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Allows designers to develop highly effective RISC-like code for fast development time

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Instruction packing:

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Gives code size equivalence for eight instructions executed serially or in parallel

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Reduces code size, program fetches, and power consumption

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Conditional execution of most instructions:

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Reduces costly branching

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Increases parallelism for higher sustained performance

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Efficient code execution on independent functional units:

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Industry's most efficient C compiler on DSP benchmark suite

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Industry's first assembly optimizer for fast development and improved parallelization

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8-/16-/32-bit/64-bit data support, providing efficient memory support for a variety of applications.

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40-bit arithmetic options which add extra precision for vocoders and other computationally intensive

applications.

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Saturation and normalization to provide support for key arithmetic operations.

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Field manipulation and instruction extract, set, clear, and bit counting support common operation found

in control and data manipulation applications.

The C66x CPU has the following additional features:

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Each multiplier can perform two 16 × 16-bit or four 8 × 8 bit multiplies every clock cycle.

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Quad 8-bit and dual 16-bit instruction set extensions with data flow support.

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Support for non-aligned 32-bit (word) and 64-bit (double word) memory accesses.

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Special communication-specific instructions have been added to address common operations in error-

correcting codes.

DM504 Datasheet(PDF) 144 Page - Texas Instruments

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