DM504 datasheet(146/211 Pages) TI1

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146

DM504

SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017

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Detailed Description

•

TMS320C66x DSP CorePac memory components:

–

A 32-KiB L1 program memory (L1P) configurable as cache and/or SRAM:

•

When configured as a cache, the L1P is a 1-way set-associative cache with a 32-byte cache

line

•

The DSP CorePac L1P memory controller provides bandwidth management, memory

protection, and power-down functions

•

The L1P is capable of cache block and global coherence operations

•

The L1P controller has an Error Detection (ED) mechanism, including necessary SRAM

•

The L1P memory can be fully configured as a cache or SRAM

•

Page size for L1P memory is 2KB

–

A 32-KiB L1 data memory (L1D) configurable as cache and / or SRAM:

•

When configured as a cache, the L1D is a 2-way set-associative cache with a 64-byte cache

line

•

The DSP CorePac L1D memory controller provides bandwidth management, memory

protection, and power-down functions

•

The L1D memory can be fully configured as a cache or SRAM

•

No support for error correction or detection

•

Page size for L1D memory is 2KB

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A 288-KiB (program and data) L2 memory, only part of which is cacheable:

•

When configured as a cache, the L2 memory is a 4-way set associative cache with a 128-byte

cache line

•

Only 256 KiB of L2 memory can be configured as cache or SRAM

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32 KiB of the L2 memory is always mapped as SRAM

•

The L2 memory controller has an Error Correction Code (ECC) and ED mechanism, including

necessary SRAM

•

The L2 memory controller supports hardware prefetching and also provides bandwidth

management, memory protection, and power-down functions.

•

Page size for L2 memory is 16KB

•

The External Memory Controller (EMC) is a bridge from the C66x CorePac to the rest of the DSP

subsystem and device. It has :

–

a 32-bit configuration port (CFG) providing access to local subsystem resources (like DSP_EDMA,

DSP_SYSTEM, and so forth) or to L3_MAIN resources accessible via the CFG address range.

–

a 128-bit slave-DMA port (SDMA) which provides accesses of system masters outside the DSP

subsystem to resources inside the DSP subsystem or C66x DSP CorePac memories, i.e. when the

DSP subsystem is the slave in a transaction.

•

The Extended Memory Controller (XMC) processes requests from the L2 Cache Controller (which

are a result of CPU instruction fetches, load/store commands, cache operations) to device resources

via the C66x DSP CorePac 128-bit master DMA (MDMA) port:

–

Memory protection for addresses outside C66x DSP CorePac generated over device L3_MAIN on

the MDMA port

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Prefetch, multi-in-flight requests

•

A DSP local Interrupt Controller (INTC) in the DSP C66x CorePac, interfaces the system events to

the DSP C66x core CPU interrupt and exceptions inputs. The DSP subsystem C66x CorePac interrupt

controller supports up to 128 system events of which 64 interrupts are external to DSP subsystem,

collected from the DSP1 dedicated outputs of the device Interrupt Crossbar.

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