DM504 datasheet(149/211 Pages) TI1

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DM504

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SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017

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Detailed Description

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L2 master interface (MIF):

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Splitter for access to memory or OCP ports

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Interleaved bank request for fast memory access

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L2 internal memories:

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16KiB ROM – IPU_ROM; used for device boot/initialization

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64KiB banked RAM – IPU_RAM

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L2 MMU (IPU_MMU): 32 entries with Table Walking Logic (TWL)

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Wake-up generator (IPU_WUGEN): Generates wake-up request from external interrupts

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Two OCP ports at IPU boundary (connected to the L3_MAIN interconnect):

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Master port – allows the IPU to access system resources (memories and peripherals)

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Slave port – allows other requestors to access a part of the IPU internal memory space

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Power management:

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Local power-management control: Configurable through the IPU_WUGEN registers.

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Two sleep modes supported by Cortex-M4, controlled by its integrated interrupt controller (NVIC).

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Cortex-M4 system is clock-gated in both sleep modes.

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NVIC interrupt interface stays awake.

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Supports L1 cache and L2 memories retention.

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Error-Correcting Code (ECC) supported for both L1 unicache and L2 RAM

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Debug/emulation features supported

For more information, see chapter Dual Cortex-M4 IPU Subsystem of the device TRM.

6.5

EVE

The embedded vision engine (EVE) module is a programmable imaging and vision processing engine,

intended for use in devices that serve customer electronics imaging and vision applications. Its

programmability meets late-in-development or post-silicon processing requirements, and lets third parties

or customers add differentiating features in imaging and vision products.

The device includes one instantiation of the EVE engine. A single EVE module consists of an ARP32

scalar core, a vector coprocessor (VCOP) vector core, and an Enhanced DMA (EDMA3) controller.

The EVE engine includes the following main features:

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Two 128-bit interconnect initiator ports used for:

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Paging between system-level memory (L3 SRAM/DDR) and EVE memory (primarily IBUF, WBUF)

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ARP32 program fetches to system memory (through program cache)

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ARP32 load or store requests to system memory

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ARP32 program cache-related read requests, including prefetch/preload requests

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128-bit interconnect target port used for system-level host or DMA access to EVE memory or MMR

space

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Scalar core (ARP32) with the following features:

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32KB program cache (direct mapped and prefetch)

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32KB data memory (DMEM)

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Vector core (VCOP):

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32KB working buffer (WBUF)

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16KB image buffer low copy A (IBUFLA)

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16KB image buffer low copy B (IBUFLB)

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16KB image buffer high copy A (IBUFHA)

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16KB image buffer high copy B (IBUFHB)

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EDMA channel controller (EDMACC): 128 PaRAM entries, 2 Queues

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EDMA transfer controllers: two instances, 2k FIFO each

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