DM504 datasheet(151/211 Pages) TI1

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DM504

www.ti.com

SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017

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Detailed Description

6.6

Memory Subsystem

6.6.1

EMIF

The EMIF module provides connectivity between DDR memory types and manages data bus read/write

accesses between external memory and device subsystems which have master access to the L3_MAIN

interconnect and DMA capability.

The EMIF module has the following capabilities:

•

Supports JEDEC standard-compliant LPDDR2/DDR2-SDRAM and DDR3/DDR3L-SDRAM memory

types

•

2-GiB SDRAM address range over one chip-select

•

Supports SDRAM devices with one, two, four or eight internal banks

•

Supports SDRAM devices with single die (one chip select supported)

•

Supports SDRAM devices with single or dual die packages

•

Data bus widths:

–

128-bit L3_MAIN (system) interconnect data bus width

–

32-bit SDRAM data bus width

–

16-bit SDRAM data bus width used in narrow mode

•

Supported CAS latencies:

–

DDR3: 5, 6, 7, 8, 9, 10 and 11

–

DDR2: 2, 3, 4, 5, 6 and 7

–

LPDDR2: 3, 4, 5, 6, 7, and 8

•

Supports 256-, 512-, 1024-, and 2048-word page sizes

•

Supported burst length: 8

•

Supports sequential burst type

•

SDRAM auto initialization from reset or configuration change

•

Supports self refresh and power-down modes for low power

•

Partial array self-refresh mode for low power when DDR3 is used

•

Output impedance (ZQ) calibration for DDR3

•

Supports on-die termination (ODT) for DDR2 and DDR3

•

Supports prioritized refresh

•

Programmable SDRAM refresh rate and backlog counter

•

Programmable SDRAM timing parameters

•

Write and read leveling/calibration and data eye training for DDR3

•

ECC on the SDRAM data bus:

–

7-bit ECC over 32-bit data

–

6-bit ECC over 16-bit data when narrow mode is used

–

1-bit error correction and 2-bit error detection

–

Programmable address ranges to define ECC protected region

–

ECC calculated and stored on all writes to ECC protected address region

–

ECC verified on all reads from ECC protected address region

–

Statistics for 1-bit ECC and 2-bit ECC errors

–

The total width of the ECC DDR data bus is 8 bits

The EMIF module does not support:

•

Burst chop for DDR3

•

Interleave burst type

•

Auto precharge because of better Bank Interleaving performance

DM504 Datasheet(PDF) 151 Page - Texas Instruments

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