DM504 datasheet(155/211 Pages) TI1

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DM504

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SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017

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Detailed Description

The EDMA can also perform transfers between external memories and between device subsystems

internal memories, with some performance loss caused by resource sharing between the read and write

ports.

EDMA controller is based on two major principal blocks:

•

EDMA third-party channel controller (EDMA_TPCC)

•

EDMA third-party transfer controller (EDMA_TPTC)

The EDMA_TPCC channel controller has following features:

•

Fully orthogonal transfer description:

–

Three transfer dimensions.

–

A-synchronized transfers: one-dimension serviced per event.

–

AB-synchronized transfers: two-dimensions serviced per event.

–

Independent indexes on source and destination.

–

Chaining feature allows a 3-D transfer based on a single event.

•

Flexible transfer definition:

–

Increment or FIFO transfer addressing modes.

–

Linking mechanism allows automatic PaRAM set update.

–

Chaining allows multiple transfers to execute with one event.

•

Interrupt generation for the following:

–

Transfer completion.

–

Error conditions.

•

Debug visibility:

–

Queue water marking/threshold.

–

Error and status recording to facilitate debug.

•

64 DMA request channels:

–

Event synchronization.

–

Chain synchronization (completion of one transfer triggers another transfer).

•

Eight QDMA channels:

–

QDMA channels trigger automatically upon writing to a parameter RAM (PaRAM) set entry.

–

Support for programmable QDMA channel to PaRAM mapping.

•

512 PaRAM sets:

–

Each PaRAM set can be used for a DMA channel, QDMA channel, or link set.

•

Two transfer controllers/event queues.

•

16 event entries per event queue.

•

Memory protection support:

–

Proxy memory protection for TR submission.

–

Active memory protection for accesses to PaRAM and registers.

The EDMA_TPTC transfer controller has the following features:

•

Two transfer controllers (TC).

•

128-bit wide read and write ports per TC.

•

Up to four in-flight transfer requests (TRs).

•

Programmable priority level.

•

Supports two-dimensional transfers with independent indexes on source and destination

(EDMA_TPCC manages the 3rd dimension).

•

Support for increment or constant addressing mode transfers.

•

Interrupt and error support.

•

Memory-Mapped Register (MMR) bit fields are fixed position in 32-bit MMR regardless of

endianness.

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