DM504 datasheet(157/211 Pages) TI1

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DM504

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SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017

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Detailed Description

•

Ancillary data capture support

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For 16-bit input, ancillary data may be extracted from any single channel

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For 8-bit time interleaved input, ancillary data can be chosen from the Luma channel, the Chroma

channel, or both channels

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Horizontal blanking interval data capture only supported when using discrete syncs (VSYNC +

HSYNC or VSYNC + HBLANK)

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Ancillary data extraction supported on multichannel capture as well as single source streams

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Format conversion and scaling

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Programmable color space conversion

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YUV422 to YUV444 conversion

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YUV444 to YUV422 conversion

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YUV422 to YUV420 conversion

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YUV422 Source: YUV422 to YUV422, YUV422 to YUV420, YUV422 to YUV444, YUV422 to

RGB888

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Supports RAW to RAW (no processing)

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Scaling and format conversions do not work for multiplexed input

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Supports up to 2047 pixels wide input - when scaling is engaged

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Supports up to 3840 pixels wide input - when only chroma up/down sampling is engaged, without

scaling

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Supports up to 4095 pixels wide input - without scaling and chroma up/down sampling

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The maximum supported input resolution is further limited by pixel clock and feature-dependent

constraints

For more information, see chapter Video Input Port of the device TRM.

6.10.2 DSS

The Display Subsystem (DSS) provides the logic to interface display peripherals. DSS integrates a DMA

engine as part of DISPC module, which allows direct access to the memory frame buffer. Various pixel

processing capabilities are supported, such as: color space conversion, filtering, scaling, blending, color

keying, etc.

The supported display interfaces are:

•

One parallel CMOS output, which can be used for MIPI® DPI 2.0, or BT-656 or BT-1120.

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One TV output, which is connected to the internal Video Encoder module (VENC). The VENC drives a

single video digital-to-analog converter (SD_DAC) supporting composite video mode.

The modules integrated in the display subsystem are:

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Display controller (DISPC), with the following main features

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One direct memory access (DMA) engine

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One graphics pipeline (GFX), two video pipelines (VID1 and VID2), and one write-back pipeline

(WB)

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Two overlay managers

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Active Matrix color support for 12/16/18/24-bit (truncated or dithered encoded pixel values)

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One Video Port (VP) with programmable timing generator to support:

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DPI: up to 165 MHz pixel clock video formats defined in CEA-861-E and VESA DMT standards

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VENC: NTSC/PAL standards with 60Hz/50Hz refresh rates

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Supported maximum FrameBuffer width of 4096 for all pixel formats

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Configurable output mode: progressive or interlaced

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Selection between RGB and YUV422 output pixel formats (YUV4:2:2 only available when BT-656

or BT-1120 output mode is enabled)

For more information, see section Display Controller in chapter Display Subsystem of the device TRM.

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