DM504 datasheet(159/211 Pages) TI1

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DM504

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SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017

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Detailed Description

•

TIMER1 (1-ms tick) includes a specific function to generate accurate tick interrupts to the operating

system and it belongs to the PD_WKUPAON domain.

•

TIMER2 through TIMER8 belong to the PD_COREAON module.

Each timer can be clocked from the system clock (19.2, 20, or 27 MHz) or the 32-kHz clock. Select the

clock source at the power, reset, and clock management (PRCM) module level.

Each timer provides an interrupt through the device IRQ_CROSSBAR.

The following are the main features of the GP timer controllers:

•

Level 4 (L4) slave interface support:

–

32-bit data bus width

–

32-/16-bit access supported

–

8-bit access not supported

–

10-bit address bus width

–

Burst mode not supported

–

Write nonposted transaction mode supported

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Interrupts generated on overflow, compare, and capture

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Free-running 32-bit upward counter

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Compare and capture modes

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Autoreload mode

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Start and stop mode

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Programmable divider clock source (2n, where n = [0:8])

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Dedicated input trigger for capture mode and dedicated output trigger/PWM signal

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Dedicated GP output signal for using the TIMERi_GPO_CFG signal

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On-the-fly read/write register (while counting)

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1-ms tick with 32.768-Hz functional clock generated (only TIMER1)

For more information, see section General-Purpose Timers in chapter Timers of the device TRM.

6.10.5.2 32-kHz Synchronized Timer (COUNTER_32K)

The 32-kHz synchronized timer (COUNTER_32K) is a 32-bit counter clocked by the falling edge of the 32-

kHz system clock.

The main features of the 32-kHz synchronized timer controller are:

•

L4 slave interface (OCP) support:

–

32-bit data bus width

–

32-/16-bit access supported

–

8-bit access not supported

–

16-bit address bus width

–

Burst mode not supported

–

Write nonposted transaction mode not supported

•

Only read operations are supported on the module registers; no write operation is supported (no

error/no action on write).

•

Free-running 32-bit upward counter

•

Start and keep counting after power-on reset

•

Automatic roll over to 0; highest value reached: 0xFFFF FFFF

•

On-the-fly read (while counting)

For more information, see section 32-kHz Synchronized Timer (COUNTER_32K) in chapter Timers of the

device TRM.

DM504 Datasheet(PDF) 159 Page - Texas Instruments

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