DM504 datasheet(160/211 Pages) TI1

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DM504

SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017

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Detailed Description

6.10.6 I2C

The device contains five multimaster inter-integrated circuit (I2C) controllers (I2Ci modules, where i = 1, 2)

each of which provides an interface between a local host (LH), such as a digital signal processor (DSP),

and any I2C-bus-compatible device that connects through the I2C serial bus. External components

attached to the I2C bus can serially transmit and receive up to 8 bits of data to and from the LH device

through the 2-wire I2C interface.

Each multimaster I2C controller can be configured to act like a slave or master I2C-compatible device.

For more information, see section Multimaster I2C Controller in chapter Serial Communication Interfaces

of the device TRM.

6.10.7 UART

The UART is a simple L4 slave peripheral that utilizes the EDMA for data transfer or IRQ polling via CPU.

There are 3 UART modules in the device. Each UART can be used for configuration and data exchange

with a number of external peripheral devices or interprocessor communication between devices.

6.10.7.1 UART Features

The UARTi (where i = 1 to 3) include the following features:

•

16C750 compatibility

•

64-byte FIFO buffer for receiver and 64-byte FIFO for transmitter

•

Programmable interrupt trigger levels for FIFOs

•

Baud generation based on programmable divisors N (where N = 1…16,384) operating from a fixed

functional clock of 48 MHz or 192 MHz

Oversampling is programmed by software as 16 or 13. Thus, the baud rate computation is one of two

options:

•

Baud rate = (functional clock / 16) / N

•

Baud rate = (functional clock / 13) / N

•

This software programming mode enables higher baud rates with the same error amount without

changing the clock source

•

Break character detection and generation

•

Configurable data format:

–

Data bit: 5, 6, 7, or 8 bits

–

Parity bit: Even, odd, none

–

Stop-bit: 1, 1.5, 2 bit(s)

•

Flow control: Hardware (RTS/CTS) or software (XON/XOFF)

•

The 48 MHz functional clock option allows baud rates up to 3.6Mbps

•

The 192 MHz functional clock option allows baud rates up to 12Mbps

For more information, see section UART in chapter Serial Communication Interfaces of the device TRM.

6.10.8 McSPI

The McSPI is a master/slave synchronous serial bus. There are four separate McSPI modules (SPI1,

SPI2, SPI3, and SPI4) in the device. All these four modules are able to work as both master and slave

and support the following chip selects:

•

McSPI1: spi1_cs[0], spi1_cs[1], spi1_cs[2], spi1_cs[3]

•

McSPI2: spi2_cs[0], spi2_cs[1]

•

McSPI3: spi3_cs[0], spi3_cs[1]

•

McSPI4: spi4_cs[0]

The McSPI modules include the following main features:

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