DM504 datasheet(148/211 Pages) TI1

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148

DM504

SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017

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Detailed Description

Fore more information about C66x debug/trace support, see chapter On-Chip Debug Support of the

device TRM.

6.4

IPU

The Imaging Processor Unit (IPU) subsystem contains two ARM® Cortex-M4 cores (IPU_C0 and IPU_C1)

that share a common level 1 (L1) cache (called unicache). The two Cortex-M4 cores are completely

homogeneous to one another. Any task possible using one Cortex-M4 core is also possible using the

other Cortex-M4 core. Both Cortex-M4 cores could be used for tasks such as running RTOS, controlling

ISP, SIMCOP, DSS, and other functions. It is software responsibility to distribute the various tasks

between the Cortex-M4 cores for optimal performance. The integrated interrupt handling of the IPU

subsystem allows it to function as an efficient control unit.

IPU is the boot master of this device with its own boot ROM.

The key features of the IPU subsystem are:

•

Two ARM Cortex-M4 microprocessors (IPU_C0 and IPU_C1):

–

ARMv7-M and Thumb®-2 instruction set architecture (ISA)

–

ARMv6 SIMD and digital signal processor (DSP) extensions

–

Single-cycle MAC

–

Integrated nested vector interrupt controller (NVIC) (also called IPU_Cx_INTC, where x = 0, 1)

–

Integrated bus matrix:

•

Bus arbiter

•

Bit-banding – atomic bit manipulation

•

Write buffer

•

Memory interface (I and D) plus system interface (S) and private peripheral bus (PPB)

–

Registers:

•

Thirteen general-purpose 32-bit registers

•

Link register (LR)

•

Program counter (PC)

•

Program status register, xPSR

•

Two banked SP registers

–

Integrated power management

–

Extensive debug capabilities

•

Unicache interface:

–

AHBLite to unicache interface

–

Instruction and data interface

–

Supports interleaved Cortex-M4 requests

•

L1 cache (IPU_UNICACHE):

–

32KiB divided into 16 banks

–

4-way

–

Runs at twice the Cortex-M4 CPU frequency

–

Cache configuration lock/freeze/preload

–

Internal MMU:

•

16-entry region-based address translation

•

Read/write control and access type control

•

Runs at twice the Cortex-M4 CPU frequency

•

Execute Never (XN) MMU protection policy

•

Little-endian format

–

OCP port for configuration and cache maintenance

•

Subsystem counter timer module (SCTM) connected to unicache

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