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DM504 Datasheet(PDF) 150 Page - Texas Instruments

Part # DM504
Description  SoC for Vision Analytics 12mm Package (ABE) Silicon Revision 2.0
PDF  211 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DM504 Datasheet(HTML) 150 Page - Texas Instruments

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DM504
SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017
www.ti.com
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Detailed Description
Copyright © 2016–2017, Texas Instruments Incorporated
•
Memory Management Units (MMUs):
–
32-entry TLB per MMU
–
Page walking with hardware
–
EDMA accesses and ARP32 program or data accesses to system memory space
–
Can limit EVE accesses to desired subset of system addresses
•
Configuration interconnect for MMR and debug accesses
•
High-performance interconnect for high throughput and high concurrency data transfers between
connected endpoints
•
Multiple interrupts for interrupt mapping, DMA event mapping, and interprocessor handshaking
•
Support for slave idle and master standby protocols for clock gating
•
No support for retention and memory array off modes
•
Error detection on all memories:
–
Single bit error detect on DMEM, WBUF, IBUFLA, IBUFLB, IBUFHA, and IBUFHB
–
Double bit error detect on program cache
•
Invalid instruction detection in the two processor units (ARP32 and VCOP)
•
Debug support:
–
Subsystem Counter Timer Module (SCTM) for counting and measuring of VCOP, EVE program
cache, and EDMA performance-related state
–
Software Messaging System Event Trace (SMSET) for trace of software messages and hardware
events
–
ARP32 debug support: State visibility, breakpoint, run control, cross-triggering
–
VCOP debug support: State visibility and run control
•
Interprocessor communication: Internal Mailbox for DSP/EVE communication
For more information, see chapter Embedded Vision Engine of the device TRM.



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