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Comparator module
PRELIMINARY V1.8
105
17.3.
Block Diagram
Figure 39.
Comparator Module Block Diagram
17.4.
Comparator Control Register
The comparator control register contains two bits. The enable bit 0 turns on the power
and clock to the comparator and automatically redirects the DI input of the SSTM to go
from the DI pad input to the comparator output cmpout. The analog input of the DI
(P3.5) is connected to the cmp_in1 of the comparator. Note: The user should disable the
digital input of the P3.5 port pin (PCR bit 4). The cmpout bit 1 of the comparator control
register allows the user to read the comparator output.
Address
85H
Bit Address
BIT
7654321
0
NAME
cmpout
enable
Definition
comparator
output
value
1-enable the
comparator:
DI pad > cmp1_in
cmpout> DI
SSTM
0-disable the
comparator:
DI pad > DI SSTM
Reset Value
0000000
0
+
COMPARATOR
DI pad
DIREF
DI SSTM
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