8101 datasheet(18/172 Pages) LSI

18 / 172 page

1-2

Introduction

internal 16-bit registers that can be accessed through the register

interface. These registers contain conﬁguration inputs, status outputs,

and management counter results.

The 8101/8104 is ideal as an Ethernet controller for Gigabit Ethernet

switch ports, uplinks, backbones, and adapter cards.

1.2 Features

The 8101/8104 provides the following features.

• Pin-compatible upgrade of 8100

• Combined Ethernet MAC and 8B10B PCS

• 1000 Mbits/s data rate

• 64-bit, 66 MHz external bus interface (4 Gbits/s bandwidth)

• 10-bit interface to external SerDes chip

• 16-bit interface to internal registers and management counters

• Full RMON, SNMP, and Ethernet management counter support

• Independent receive and transmit FIFOs with programmable

watermarks

–

16 Kbytes receive FIFO size

–

4 Kbytes transmit FIFO size

• AutoNegotiation algorithm on chip

• Full duplex only

• Flow control per IEEE 802.3x

• Automatic CRC generation and checking

• Automatic packet error discarding

• Programmable transmit start threshold

• Interrupt capability

• Support for ﬁber and short haul copper media

• 3.3 V power supply, 5 V tolerant inputs

• IEEE 802.3 and 802.3z speciﬁcation compliant

8101 Datasheet(PDF) 18 Page - LSI Computer Systems