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8101 Datasheet(PDF) 55 Page - LSI Computer Systems

Part # 8101
Description  Gigabit Ethernet Controller
PDF  172 Pages
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Manufacturer  LSI [LSI Computer Systems]
Direct Link  http://www.lsicsi.com
Logo LSI - LSI Computer Systems

8101 Datasheet(HTML) 55 Page - LSI Computer Systems

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Receive Status Word
2-37
Copyright © 2000–2001 by LSI Logic Corporation. All rights reserved.
2.14 Receive Status Word
A 32-bit status word can be appended to the end of each good receive
data packet and stored in the receive FIFO. This status word contains a
byte count and error information for the receive data packet.
2.14.1 Format
The format for the status word is shown in Table 2.11. The upper sixteen
bits contain the actual byte count for the packet and the lower sixteen
bits contain the status information related to the packet. Note that the
endian select bit affects the byte order of the status word in the same
way that it affects the normal data byte order on the system interface.
The byte count value in the status word (upper sixteen bits) is the total
number of actual bytes in the received packet minus the preamble, SFD,
and CRC bytes. The byte count is independent of whether the receive
MAC has stripped the preamble or CRC. If the packet overflows the
receive FIFO, the byte count stops counting at the moment that the
receive FIFO overflow has been detected and the remaining bytes on the
incoming packet are not counted.
Table 2.11
Receive Status Word Definition
RXD31
RXD16
BC[15:0]
RXD15
RXD0
RESERVED
MPKT
CWRD
OSIZE USIZE OVFL
CRC
Symbol
Name
Definition
Position on
RXD[31:0]1
BC[15:0]
Byte count
Contains actual byte count of the receive packet
RXD[31:16]
–
–
Reserved
RXD[15:6]
MPKT
Multiple packet
reject
1 = RX FIFO full and multiple consecutive packets
were discarded. Status word indicates error
condition for first packet of discarded group.
RXD5
CWRD
Codeword error
1 = Receive packet has PCS coding error
RXD4



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