8101 datasheet(91/172 Pages) LSI

91 / 172 page

4-3

4.1.2 Interrupt

An interrupt is triggered when certain output status bits change state.

These bits are called interrupt bits and are designated as R/LLI, R/LHI,

and R/LTI bits, as described in the previous section. The interrupt bits

reside in “Register 11–Status 1‚" Section 4.3.12, and “Register 112–115–

Counter Half Full 1-4‚" Section 4.3.23,. Interrupt bits automatically latch

Table 4.1

Bit Types

Deﬁnition

Symbol

Name

Write Cycle

Read Cycle

Write

Input

No operation, output not valid

Read

No operation, input ignored

Output

R/W

Read/Write

Input

Ouput

R/W

Read/Write

Self Clearing

Input

Clears itself after operation

completed

Ouput

R/LL

R/LLI

Read, Latch when 0

Read, Latch when

0, Assert Interrupt

No operation latching

Output

Input ignored when bit goes to 0,

bit latched, and interrupt asserted

(if not masked)

When bit is read, bit updated and

interrupt cleared

R/LH

R/LHI

Read/write

Read/write, latch

HIGH with interrupt

No operation, input ignored

Output

When bit goes to 1, bit latched &

interrupt asserted (if not masked)

When bit is read, bit updated and

interrupt cleared

R/LT

R/LTI

Read, Latch on

Transition

Read, Latch on

Transition with

interrupt

No operation, input ignored

Output

When bit transitions, bit latched and

interrupt asserted (if not masked)

When bit is read, bit updated and

interrupt cleared

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