8101 datasheet(15/172 Pages) LSI

15 / 172 page

Tables

2.1

Length/Type Field Deﬁnition

2-8

2.2

Byte Enable Pin vs. Valid Byte Position

2-10

2.3

TXRC Bit and TXCRCn Pin Logic

2-16

2.4

Transmit IPG Selection

2-16

2.5

Multicast Address Filter Map

2-19

2.6

Receive Maximum Packet Size Selection

2-21

2.7

8B10B Coding Table

2-27

2.8

10B Deﬁned Ordered Sets

2-28

2.9

Transmit Discard Conditions

2-34

2.10

Receive Discard Conditions

2-35

2.11

Receive Status Word Deﬁnition

2-37

2.12

AutoNegotiation Status Bits

2-41

2.13

Reset Description

2-47

2.14

Counter Deﬁnition

2-49

2.15

Counter Maximum Packet Size Selection

2-58

4.1

4-3

4.2

4-4

4.3

4-10

5.1

Compatible SerDes Devices

5-3

5.2

Reset Procedure

5-6

5.3

SerDes Loopback Procedure

5-7

5.4

AutoNegotiation Power Up Procedure

5-8

5.5

MIB Objects vs. Counter Location for RMON

Statistics Group MIB (RFC 1757)

5-10

5.6

MIB Objects vs. Counter Location for SNMP

Interface Group MIB (RFC 1213 and 1573)

5-11

5.7

MIB Objects vs. Counter Location for Ethernet-Like

Group MIB (RFC 1643)

5-13

5.8

MIB Objects vs. Counter Location For Ethernet MIB

(IEEE 802.3z, Clause 30)

5-14

6.1

DC Electrical Characteristics

6-2

6.2

Input Clock Timing Characteristics

6-4

6.3

Transmit System Interface Timing Characteristics

6-5

6.4

Receive System Interface Timing Characteristics

6-7

6.5

System Interface RXDC/TXDC Timing Characteristics

6-10

6.6

Transmit 10-Bit PHY Interface Timing Characteristics

6-11

8101 Datasheet(PDF) 15 Page - LSI Computer Systems

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