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8101 Datasheet(PDF) 71 Page - LSI Computer Systems

Part # 8101
Description  Gigabit Ethernet Controller
PDF  172 Pages
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Manufacturer  LSI [LSI Computer Systems]
Direct Link  http://www.lsicsi.com
Logo LSI - LSI Computer Systems

8101 Datasheet(HTML) 71 Page - LSI Computer Systems

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Counters
2-53
Copyright © 2000–2001 by LSI Logic Corporation. All rights reserved.
42
dot3StatsLateCollisions
TX
Packets that encounter a late collision,
i.e. encountered collisions more than
512-bit times into transmitted packet.
A late collision is counted twice:
as a collision and a late collision.
Since controller is Full Duplex only,
this counter is undefined.
32
0b11010010
0b11010011
43
dot3StatsExcessiveCollisions
TX
Packets not successfully transmitted
after more than 15 collisions
(ie: attempt value=16).
Since controller is Full Duplex only,
this counter is undefined.
32
0b11010100
0b11010101
dot3StatsInternalMacTransmitErrors
TX
Packets with transmit FIFO underflow
error.
Equivalent to "ifOutDiscards"
Use Ctr. #34
44
dot3StatsCarrierSenseErrors
TX
Carrier sense dropout errors, i.e.
number of times that carrier sense is
not asserted or deasserted during
packet transmission, without a collision.
This counter is only incremented once
per packet, regardless of the number of
dropout errors in the packet.
There is no CRS loopback in 8B10B
Ethernet, so this counter is undefined.
32
0b11010110
0b11010111
dot3StatsFrameTooLongs
RX
Packets of length > Max_Packet_Length
with no other errors.
Equivalent to "etherStatsOversizePkts"
Use Ctr. #8
dot3StatsInternalMacReceiveErrors
RX
Packets with receive FIFO overflow
error.
Equivalent to "etherStatsDropEvents"
Use Ctr. #1
Ethernet MIB
(IEEE 802.3z Clause 30)
44
aFramesTransmittedOK
TX
All packets, good only.
Equivalent to
"etherStatsPkts_TX - ifOutErrors"
32
Use Ctr.
#19 through
35
aSingleCollisionFrames
TX
Packets successfully transmitted after
one and only one collision (ie: attempt
value = 2).
Equivalent to
"dot3StatsSingleCollisionFrames"
Use Ctr. #38
Table 2.14
Counter Definition (Cont.)
Counter
Number
Counter Name
(MIB Object Name)
Counter Description
RX/TX
Definition
Size
(Bits)
Register
Address
REGAD[7:0]
(Low/High)



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