8101 datasheet(92/172 Pages) LSI

92 / 172 page

4-4

Registers

themselves and assert the interrupt pin, REGINT. Interrupt bits stay

latched until they are read. When interrupt bits are read, the interrupt pin

REGINT is deasserted and the interrupt bits that caused the interrupt are

updated to their current value.

Each interrupt bit can be individually masked and subsequently removed

as an interrupt bit. Setting the appropriate mask register bits in “Register

14–Status Mask 1‚" Section 4.3.13, register and “Registers 120–123–

Counter Half Full Mask 1-4‚" Section 4.3.24, preform this function.

4.1.3 Register Structure

The Controller has 136 internal 16-bit registers. 22 registers are available

for setting conﬁguration inputs and reading status outputs. The remaining

114 registers are associated with the management counters. The

location of all registers is described in Table 4.2 Register Address Table.

The deﬁnition of each bit for each register is described in Section 4.3.1

through Section 4.3.25.

4.2 Register Addresses

Table 4.2 lists the register number, register address, register name, and

the paragraph that describes the register. Table 4.3 lists the register

default values.

Table 4.2

Numbers

Address

(REGAD[7:0]

Pins)

Paragraph

Number

0b00000000

MAC Address 1

4.3.1

0b00000001

MAC Address 2

4.3.2

0b00000010

MAC Address 3

4.3.3

0b00000011

MAC Address Filter 1

4.3.4

0b00000100

MAC Address Filter 2

4.3.5

0b00000101

MAC Address Filter 3

4.3.6

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