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8101 Datasheet(PDF) 19 Page - LSI Computer Systems |
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8101 Datasheet(HTML) 19 Page - LSI Computer Systems |
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19 / 172 page  8101/8104 Gigabit Ethernet Controller 2-1 Copyright © 2000–2001 by LSI Logic Corporation. All rights reserved. Chapter 2 Functional Description This chapter provides a high level description of the 8101/8104 Gigabit Ethernet Controller and consists of the following sections: • Section 2.1, “Overview” • Section 2.2, “Transmit Data Path” • Section 2.3, “Receive Data Path” • Section 2.4, “Register Structure” • Section 2.5, “Ethernet Frame Format” • Section 2.6, “System Interface” • Section 2.7, “Transmit MAC” • Section 2.8, “Receive MAC” • Section 2.9, “Transmit FIFO” • Section 2.10, “Receive FIFO” • Section 2.11, “8B10B PCS” • Section 2.12, “10-Bit PHY Interface” • Section 2.13, “Packet Discard” • Section 2.14, “Receive Status Word” • Section 2.15, “AutoNegotiation” • Section 2.16, “Flow Control” • Section 2.17, “MAC Control Frames” • Section 2.18, “Reset” • Section 2.19, “Counters” • Section 2.20, “Loopback” • Section 2.21, “Test Modes” |
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