8101 datasheet(66/172 Pages) LSI

66 / 172 page

2-48

Functional Description

All counters are 32 bits wide. To obtain each 32-bit counter result,

perform a read operation over the register interface. The address

locations for each counter are shown in both Table 2.14 and Table 4.2.

For the two 16-bit register locations associated with each 32-bit counter,

the register with the lower value address always contains the least

signiﬁcant 16 bits of the counter result. Thus, C0 of the lower value

address register is the counter LSB; C15 of the higher value address

When a counter read operation is initiated, the 32-bit counter result to be

accessed is transferred to two internal 16-bit holding registers. These

holding registers freeze and store the counter result for the duration of

the read operation, while allowing the internal counter to continue to

increment if needed.

When a counter is read, the count can, under program control, be

automatically reset to zero or remain unchanged. Counters can be

programmed to either stop counting when they reach their maximum

count or roll over. Burst reading is only supported for the low and high

value address of the same counter. To read the value of multiple

counters, either REGCSn or REGRDn must be deasserted then

reasserted.

Each counter has an associated status bit that is set when the counter

becomes half full. These status bits can be individually programmed to

cause an interrupt.

The counter set in Table 2.14 includes the packet and octet statistics for

the transmit and receive sides. The RMON speciﬁcation literally states

that packet and octet counters should only tabulate received information.

This is sometimes interpreted to mean both transmitted and received

information because Ethernet was originally a shared media protocol. As

such, packet and octet counters for both transmit and receive are

available in the controller, and the transmit and receive packet and octet

counts can be summed together if desired.

The exact correspondence of the actual MIB objects from the IETF and

IEEE speciﬁcations to the actual controller counters locations is

described in Chapter 5, Application Information.

8101 Datasheet(PDF) 66 Page - LSI Computer Systems