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8101 Datasheet(PDF) 32 Page - LSI Computer Systems |
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8101 Datasheet(HTML) 32 Page - LSI Computer Systems |
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32 / 172 page ![]() 2-14 Functional Description Copyright © 2000–2001 by LSI Logic Corporation. All rights reserved. RXABORT definition bit in “Register 9–Configuration 3‚" Section 4.3.10, also programs the controller to discard either the data packet and its status word or just the data packet exclusive of the status word. The RXOEn signal, when asserted, places certain receive outputs in the high-impedance state. RXOEn affects the RXD[31:0], RXBE[3:0], RXSOF, and RXEOF output pins. 2.6.4 Bus Width Setting the BUSSIZE bit in “Register 10–Configuration 4‚" Section 4.3.11, changes the receive word width from 32-bits to 16-bits. When the bus width is configured to 16-bits, the receive system interface data outputs appear on RXD[15:0] and the data words are now 16-bits wide instead of 32-bits wide. Note: The transmit word width can be adjusted by appropriately setting the transmit byte enable inputs, TXBE[3:0], as described in Table 2.2. 2.6.5 System Interface Disable To disable the system interface, set the SINTF_DIS bit in “Register 9– Configuration 3‚" Section 4.3.10. When the system interface is disabled, the controller: • Places all system interface outputs in the high-impedance state (TXWMn[1:2], TXDC, RXD[31:0], RXBE[3:0], RXSOF, RXEOF, RXWM1/2, RXDC) • Ignores all inputs (SCLK, TXENn, TXD[31:0], TXBE[3:0], TXSOF, TXEOF, CLR_TXDC, FCNTRL, TXCRCn, RXENn, RXOEn, CLR_RXDC, RXABORT) • Transmits /C/ (see Table 2.8) ordered sets with the remote fault bits RF[1:0] = 0b10 over the 10-bit PHY interface outputs |
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