8101 datasheet(82/172 Pages) LSI

82 / 172 page

3-4

Signal Descriptions

RXD[31:0]

Receive Data

Output

This output bus contains the 32-bit received data word

that is clocked out on the rising edge of the system

interface clock, SCLK.

RXDC

Receive Packet Discard

Output

When HIGH, device detects that current packet being

output on the system interface has an error and should

be discarded. When LOW, no discard.

Asserting the RXABORT pin or setting the AUTORXAB

bit in “Register 9–Conﬁguration 3‚" Section 4.3.10,

automatically discards the packet being output. RXDC is

clocked out on the rising edge of the system clock, SCLK.

If AutoClear mode is not enabled, this output is latched

HIGH and stays latched until cleared with the assertion

of the CLR_RXDC pin. If AutoClear mode is enabled, this

output is latched HIGH and automatically clears itself

LOW two clock cycles after RXEOF is asserted. RXDC

can also be cleared with RXABORT if programmed to do

so.

RXENn

Receive Enable

Input

This input must be asserted active LOW to enable the

current data word to be clocked out of the receive FIFO

on RXD[31:0]. RXENn is clocked in on the rising edge of

the system interface clock, SCLK.

RXEOF

Receive End Of Frame

Output

This output is asserted on the same clock cycle as the

last word of the packet is being read out of the receive

FIFO on RXD[31:0]. RXEOF is clocked out of the device

on the rising edge of the system interface clock, SCLK.

RXOEn

Receive Output Enable

Input

When LOW, all receive outputs are active. When HIGH,

receive outputs (RXD[31:0], RXBE[3:0], RXSOF, RXEOF)

are high-impedence.

RXSOF

Receive Start Of Frame

Output

This output is asserted on the same clock cycle as the

ﬁrst word of the packet is being read out of the receive

FIFO on RXD[31:0]. RXSOF is clocked out of the device

on the rising edge of the system interface clock, SCLK.

8101 Datasheet(PDF) 82 Page - LSI Computer Systems

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