8101 datasheet(43/172 Pages) LSI

43 / 172 page

8B10B PCS

2-25

the 8B10B PCS section. The watermarks stay asserted until the data in

the FIFO goes below the respective thresholds, and RXWM2 also stays

asserted until all end of packets (EOF) have been read out of the receive

FIFO. After the EOFs have been read out of the receive FIFO, the

watermarks cannot go active again until RXENn is deasserted.

2.10.2 RX Overﬂow

The receive FIFO overﬂow condition occurs when the receive RX FIFO

is full and additional data is still being written into it from the MAC. If the

receive FIFO overﬂows:

• The input to the RX FIFO is blocked and does not accept any more

data from the 8B10B PCS until RX FIFO space is freed up

• The data already stored in the RX FIFO for the partially loaded last

packet is normally discarded

• Any new data for the partially loaded last packet is also normally

discarded

Refer to Section 2.13, “Packet Discard” for more information about

discards. Clearing the DIS_OVF bit in “Register 8–Conﬁguration 2‚"

Section 4.3.9, programs the controller to not discard a packet corrupted

by overﬂow.

2.10.3 RX Underﬂow

The receive FIFO underﬂow condition occurs when the system interface

is attempting to read data out of the RX FIFO when it is empty. If the RX

FIFO underﬂows, any data read out of the RX FIFO while the underﬂow

condition persists is invalid, and any new data for the partially loaded last

packet is stored in the RX FIFO and is not discarded.

2.11 8B10B PCS

The 8B10B PCS has a transmit section and a receive section.

The transmit 8B10B PCS section accepts Ethernet formatted packet data

from the transmit MAC and:

• Encodes the data with the 8B10B encoder

• Adds the start of packet delimiter

8101 Datasheet(PDF) 43 Page - LSI Computer Systems