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8101 Datasheet(PDF) 53 Page - LSI Computer Systems |
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8101 Datasheet(HTML) 53 Page - LSI Computer Systems |
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53 / 172 page ![]() Packet Discard 2-35 Copyright © 2000–2001 by LSI Logic Corporation. All rights reserved. 2.13.2 Receive Discards Receive packets can be discarded if the error conditions listed in Table 2.10 are detected. The discard behavior is dependent on whether or not the packet is being output on the system interface when the discard condition is detected. If the packet containing the error is not being output on the system interface when the discard condition is detected (an internal discard) the packet is discarded, (all data from the packet containing the error is flushed from the receive FIFO). If the packet containing the error is being output on the system interface when the discard condition is detected (an external discard) the RXDC pin is asserted to indicate the error condition. Asserting the RXABORT pin or setting the AUTORXAB bit in “Register 9–Configuration 3‚" Section 4.3.10, automatically discards the packet. For both internal and external discarded packets, the appended status word is updated to reflect the discard error condition. Each of the receive discard conditions can be individually removed as a discard condition by appropriately clearing the appropriate discard bit in “Register 8–Configuration 2‚" Section 4.3.9, associated with the corresponding condition. When these bits are cleared, a packet that is afflicted with the error condition indicated by that bit is not discarded. Table 2.10 Receive Discard Conditions Discard Condition Description Receive FIFO overflow Receive FIFO full. No more data accepted from the 8B10B PCS. CRC error Receive packet has a CRC error. Undersize packet Receive packet is less than 64 bytes, exclusive of preamble and SFD. Oversize packet Receive packet is greater than maximum packet size, exclusive of preamble and SFD. PCS codeword error Receive packet contains at least one word with an 8B10BPCS coding error. RXABORT pin asserted RXABORT pin was asserted while the receive packet was read out on the system interface. The process of flushing a receive packet with RXABORT pin requires extra SCLK cycles equal to: (packet length in bytes)/8 + 6. |
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