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8101/8104 Gigabit Ethernet Controller

1-1

Chapter 1

Introduction

This chapter contains a brief introduction to the 8101/8104 Gigabit

Ethernet Controller. It consists of the following sections:

• Section 1.1, “Overview”

• Section 1.2, “Features”

1.1 Overview

The 8101/8104 Gigabit Ethernet Controller is a complete media access

controller (MAC sublayer) with integrated coding logic for ﬁber and short

haul copper media (8 bit/10 bit Physical Coding Sublayer) (8B10B PCS)

for 1000 Mbits/s Gigabit Ethernet systems.

The 8104 is functionally the same as the 8101 except that the 8104 is in

a 208-pin Ball Grid Array (BGA) package and the 8101 is in a 208-pin

Plastic Quad Flat Pack (PQFP) package

The Controller consists of a 32-bit system interface, receive/transmit First

In, First Out (FIFO) buffers, a full-duplex Ethernet Media Access

Controller (MAC), an 8 bit/10 bit PCS, a 10-bit Physical Layer Device

(PHY) interface, and a 16-bit register interface. The controller also

contains all the necessary circuitry to implement the IEEE 802.3x Flow

Control Algorithm. Flow control messages can be sent automatically

without host intervention.

The controller contains 53 counters which satisfy the management

objectives of the Remote Monitoring (RMON) Statistics Group MIB,

(RFC 1757), Simple Network Management Protocol (SNMP) Interfaces

Group (RFC 1213 and 1573), Ethernet-Like Group MIB (RFC 1643), and

Ethernet MIB (IEEE 802.3z Clause 30). The controller also contains 136

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