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8101 Datasheet(PDF) 56 Page - LSI Computer Systems |
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8101 Datasheet(HTML) 56 Page - LSI Computer Systems |
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56 / 172 page ![]() 2-38 Functional Description Copyright © 2000–2001 by LSI Logic Corporation. All rights reserved. 2.14.2 Append Options The status word is normally appended to the end of all good receive packets. However, the controller can also be programmed to store a status word in the receive FIFO for discarded packets as well as append a status word to the end of good (nondiscarded) packets. The controller can also be programmed to not append any status word at all. Setting the STSWRD [1:0] bits in “Register 7–Configuration 1‚" Section 4.3.8, select the appropriate status word option. 2.14.3 Status Word for Discarded Packets When the controller is programmed to add a status word for discarded packets, only the status word is stored in the receive FIFO for each discarded packet. The status word for a discarded packet contains an indication of the error that caused the discard. If the receive FIFO is full and more than one consecutive packet was discarded, then one more status word is stored in the receive FIFO for the next consecutive group of discarded packets. A bit is set in the status word indicating that multiple status words or multiple packets have been discarded. When a status word has the multiple discard bit set, the other status bits reflect the status of the second discarded packet only. 2.14.4 Status Word for RXABORT Packets When the RXABORT pin is asserted, both the packet data and its associated status word are normally flushed from the receive FIFO. Setting the RXAB_DEF bit in “Register 9–Configuration 3‚" Section 4.3.10, programs the controller to allow the RXABORT pin to discard the packet only and leave the status word for the discarded packet in the receive FIFO. OSIZE Oversize packet 1 = Receive packet is greater than maximum size RXD3 USIZE Undersize packet 1 = Receive packet is less than minimum size RXD2 OVFL Receive FIFO overflow 1 = Receive FIFO is full and has received additional data RXD1 CRC CRC error 1 = Receive packet has a CRC error RXD0 1. This byte order is for little endian format. Big endian format reverses this byte order. Symbol Name Definition Position on RXD[31:0]1 |
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