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FS5502 Datasheet(PDF) 110 Page - NXP Semiconductors

Part # FS5502
Description  High voltage PMIC with multiple SMPS and LDO
PDF  113 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

FS5502 Datasheet(HTML) 110 Page - NXP Semiconductors

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NXP Semiconductors
FS5502
High voltage PMIC with multiple SMPS and LDO
Tables
Tab. 1.
Ordering information ..........................................2
Tab. 2.
Pin description ...................................................4
Tab. 3.
Connection of unused pins ............................... 6
Tab. 4.
Electrical characteristics ..................................12
Tab. 5.
Main writing registers overview ....................... 13
Tab. 6.
Main reading registers overview ......................14
Tab. 7.
M_FLAG register bit allocation ........................14
Tab. 8.
M_FLAG register bit description ......................15
Tab. 9.
M_MODE register bit allocation ...................... 16
Tab. 10. M_MODE register bit description .................... 16
Tab. 11. M_REG_CTRL1 register bit allocation ............ 17
Tab. 12. M_REG_CTRL1 register bit description .......... 17
Tab. 13. M_REG_CTRL2 register bit allocation ............ 18
Tab. 14. M_REG_CTRL2 register bit description .......... 18
Tab. 15. M_CLOCK register bit allocation .....................19
Tab. 16. M_CLOCK register bit description ...................19
Tab. 17. M_INT_MASK1 register bit allocation ..............20
Tab. 18. M_INT_MASK1 register bit description ........... 21
Tab. 19. M_INT_MASK2 register bit allocation ..............22
Tab. 20. M_INT_MASK2 register bit description ........... 22
Tab. 21. M_FLAG1 register bit allocation ......................23
Tab. 22. M_FLAG1 register bit description ....................23
Tab. 23. M_FLAG2 register bit allocation ......................24
Tab. 24. M_FLAG2 register bit description ....................25
Tab. 25. M_VMON_REGx register bit allocation ........... 26
Tab. 26. M_VMON_REGx register bit description ......... 26
Tab. 27. M_LVB1_SVS register bit allocation ................27
Tab. 28. M_LVB1_SVS register bit description ..............27
Tab. 29. M_MEMORY0 register bit allocation ............... 27
Tab. 30. M_MEMORY0 register bit description ............. 28
Tab. 31. M_MEMORY1 register bit allocation ............... 28
Tab. 32. M_MEMORY1 register bit description ............. 28
Tab. 33. M_DEVICEID register bit allocation ................ 28
Tab. 34. M_DEVICEID register bit description .............. 29
Tab. 35. Fail-safe writing registers overview ................. 29
Tab. 36. Fail-safe reading registers overview ................30
Tab. 37. FS_GRL_FLAGS register bit allocation ...........30
Tab. 38. FS_GRL_FLAGS register bit description .........30
Tab. 39. FS_I_OVUV_SAFE_REACTION1 register
bit allocation .................................................... 31
Tab. 40. FS_I_OVUV_SAFE_REACTION1 register
bit description .................................................. 31
Tab. 41. FS_I_OVUV_SAFE_REACTION2 register
bit allocation .................................................... 31
Tab. 42. FS_I_OVUV_SAFE_REACTION2 register
bit description .................................................. 32
Tab. 43. FS_I_FSSM register bit allocation ...................32
Tab. 44. FS_I_FSSM register bit description .................32
Tab. 45. FS_I_SVS register bit allocation ......................33
Tab. 46. FS_I_SVS register bit description ................... 34
Tab. 47. FS_OVUVREG_STATUS register bit
allocation ......................................................... 34
Tab. 48. FS_OVUVREG_STATUS register bit
description ....................................................... 35
Tab. 49. FS_SAFE_IOS register bit allocation .............. 36
Tab. 50. FS_SAFE_IOS register bit description ............ 36
Tab. 51. FS_DIAG register bit allocation .......................37
Tab. 52. FS_DIAG register bit description .....................37
Tab. 53. FS_INTB_MASK register bit allocation ............38
Tab. 54. FS_INTB_MASK register bit description ......... 38
Tab. 55. FS_STATES register bit allocation .................. 38
Tab. 56. FS_STATES register bit description ................ 39
Tab. 57. Main OTP_REGISTERS ................................. 40
Tab. 58. Fail-safe OTP_REGISTERS ............................41
Tab. 59. Main OTP bit description .................................41
Tab. 60. Fail-safe OTP bit description ...........................46
Tab. 61. Best of supply electrical characteristics ...........52
Tab. 62. VPRE electrical characteristics ....................... 56
Tab. 63. VPRE external MOSFETs recommendation .... 58
Tab. 64. BUCK1 electrical characteristics ..................... 63
Tab. 65. BUCK3 electrical characteristics ..................... 69
Tab. 66. LDO1 electrical characteristics ........................71
Tab. 67. Manual frequency tuning configuration ............73
Tab. 68. FOUT multiplexer selection .............................74
Tab. 69. Electrical characteristics ..................................74
Tab. 70. WAKE1, WAKE2 electrical characteristics .......75
Tab. 71. INTB electrical characteristics .........................75
Tab. 72. List of interrupts from main logic ..................... 76
Tab. 73. List of interrupts from fail-safe logic ................ 76
Tab. 74. PSYNC electrical characteristics .....................78
Tab. 75. I2C message arrangement ..............................79
Tab. 76. CRC results example ...................................... 80
Tab. 77. I2C electrical characteristics ............................81
Tab. 78. Maximum ratings .............................................81
Tab. 79. Thermal ratings ............................................... 83
Tab. 80. Electrical characteristics ..................................84
Tab. 81. VCOREMON error impact configuration ..........86
Tab. 82. VCOREMON electrical characteristics ............ 86
Tab. 83. SVS offset configuration ..................................87
Tab. 84. VDDIO error impact configuration ................... 89
Tab. 85. VDDIO electrical characteristics ......................89
Tab. 86. VMONx error impact configuration .................. 90
Tab. 87. VMON1 (without ext resistor accuracy)
electrical characteristics .................................. 90
Tab. 88. Application related fail-safe fault list and
reaction ............................................................91
Tab. 89. Fault error counter configuration ..................... 92
Tab. 90. PGOOD electrical characteristics ....................93
Tab. 91. RSTB electrical characteristics ........................94
Tab. 92. Package comparison .......................................98
Tab. 93. Revision history .............................................106
Figures
Fig. 1.
Simplified application diagram of FS5502 ......... 2
Fig. 2.
Block diagram of FS5502 ..................................3
FS5502
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 4 — 27 October 2021
110 / 113



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