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FS5502 Datasheet(PDF) 112 Page - NXP Semiconductors |
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FS5502 Datasheet(HTML) 112 Page - NXP Semiconductors |
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112 / 113 page  NXP Semiconductors FS5502 High voltage PMIC with multiple SMPS and LDO Contents 1 General description ............................................ 1 2 Features and benefits .........................................1 3 Applications .........................................................2 4 Simplified application diagram .......................... 2 5 Ordering information .......................................... 2 6 Block diagram ..................................................... 3 7 Pinning information ............................................ 4 7.1 Pinning ...............................................................4 7.2 Pin description ................................................... 4 7.3 Connection of unused pins ................................6 8 Functional description ........................................8 8.1 Simplified functional state diagram ....................8 8.2 Main state machine ........................................... 8 8.3 Fail-safe state machine ..................................... 9 8.4 Power sequencing ............................................. 9 8.5 Debug mode .................................................... 11 9 Register mapping ..............................................12 10 Main register mapping ......................................13 10.1 Main writing registers overview ....................... 13 10.2 Main reading registers overview ......................14 10.3 M_FLAG register ............................................. 14 10.4 M_MODE register ............................................16 10.5 M_REG_CTRL1 register ..................................17 10.6 M_REG_CTRL2 register ..................................18 10.7 M_CLOCK register .......................................... 19 10.8 M_INT_MASK1 register ...................................20 10.9 M_INT_MASK2 register ...................................22 10.10 M_FLAG1 register ........................................... 23 10.11 M_FLAG2 register ........................................... 24 10.12 M_VMON_REGx register ................................ 26 10.13 M_LVB1_SVS register ..................................... 27 10.14 M_MEMORY0 register .....................................27 10.15 M_MEMORY1 register .....................................28 10.16 M_DEVICEID register ......................................28 11 Fail-safe register mapping ............................... 29 11.1 Fail-safe writing registers overview ..................29 11.2 Fail-safe reading registers overview ................ 30 11.3 FS_GRL_FLAGS register ................................ 30 11.4 FS_I_OVUV_SAFE_REACTION1 register ...... 31 11.5 FS_I_OVUV_SAFE_REACTION2 register ...... 31 11.6 FS_I_FSSM register ........................................ 32 11.7 FS_I_SVS register ...........................................33 11.8 FS_OVUVREG_STATUS register ....................34 11.9 FS_SAFE_IOs register .................................... 36 11.10 FS_DIAG register ............................................ 37 11.11 FS_INTB_MASK register .................................38 11.12 FS_STATES register ........................................38 12 OTP bits configuration ..................................... 40 12.1 Overview ..........................................................40 12.2 Main OTP bit description ................................. 41 12.3 Fail-safe OTP bit description ........................... 46 13 Best of supply ...................................................51 13.1 Functional description ......................................51 13.2 Best of supply electrical characteristics ........... 52 14 High voltage buck: VPRE .................................52 14.1 Functional description ......................................52 14.2 Application schematic ......................................53 14.3 Compensation network and stability ................ 53 14.4 VPRE electrical characteristics ........................56 14.5 VPRE external MOSFETs ................................58 14.6 VPRE efficiency ...............................................59 14.7 VPRE not populated ........................................60 15 Low voltage buck: BUCK1 ............................... 60 15.1 Functional description ......................................60 15.2 Application schematic: Single phase mode ......60 15.3 Compensation network and stability ................ 61 15.4 BUCK1 electrical characteristics ......................63 15.5 BUCK1 efficiency .............................................64 16 Low voltage buck: BUCK3 ............................... 65 16.1 Functional description ......................................65 16.2 Application schematic ......................................66 16.3 Compensation network and stability ................ 66 16.4 BUCK3 electrical characteristics ......................69 16.5 BUCK3 efficiency .............................................69 17 Linear voltage regulator: LDO1 ....................... 70 17.1 Functional description ......................................70 17.2 Application schematics .................................... 70 17.3 LDO1 electrical characteristics ........................ 71 18 Clock management ........................................... 71 18.1 Clock description ............................................. 71 18.2 Phase shifting .................................................. 72 18.3 Manual frequency tuning ................................. 72 18.4 Spread spectrum ............................................. 73 18.5 External clock synchronization ........................ 73 18.6 Electrical characteristics .................................. 74 19 I/O interface pins ...............................................75 19.1 WAKE1, WAKE2 ..............................................75 19.2 INTB .................................................................75 19.3 PSYNC for two FS5502 ...................................77 19.4 PSYNC for FS5502 and external PMIC ...........78 20 I2C interface ...................................................... 79 20.1 I2C interface overview .....................................79 20.2 Device address ................................................79 20.3 Cyclic redundant check ................................... 80 20.4 I2C electrical characteristics ............................81 21 Maximum ratings ...............................................81 22 Electrostatic discharge .....................................82 22.1 Human body model (JESD22/A114) ................82 22.2 Charged device model .....................................82 22.3 Discharged contact test ...................................82 23 Operating conditions ........................................ 82 24 Thermal characteristics ....................................83 25 Characteristics .................................................. 84 26 Application information ....................................85 27 Fail-safe domain description ........................... 85 27.1 Functional description ......................................85 27.2 Voltage supervisor ........................................... 86 27.2.1 VCOREMON monitoring ..................................86 27.2.2 Static voltage scaling (SVS) ............................ 87 27.2.3 VDDIO monitoring ............................................88 27.2.4 VMON1 monitoring .......................................... 89 27.3 Fault management ...........................................91 FS5502 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 27 October 2021 112 / 113 |
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