FS5502 datasheet(111/113 Pages) NXP

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NXP Semiconductors

FS5502

High voltage PMIC with multiple SMPS and LDO

Fig. 3.

Pin configuration for HVQFN56 .........................4

Fig. 4.

Simplified functional state diagram ....................8

Fig. 5.

Power sequencing (VREGx PWR_UP) ........... 10

Fig. 6.

Power up sequence example ..........................11

Fig. 7.

Debug mode entry .......................................... 12

Fig. 8.

VPRE schematic ............................................. 53

Fig. 9.

Type 2 compensation network concept ........... 54

Fig. 10.

Phase and gain margin simulation .................. 55

Fig. 11.

Transient response simulation .........................56

Fig. 12.

MOSFET gate charge definition ......................59

Fig. 13.

VPRE theoretical efficiency .............................59

Fig. 14.

BUCK1 standalone schematic .........................61

Fig. 15.

Phase and gain margin simulation .................. 62

Fig. 16.

Transient response simulation .........................63

Fig. 17.

BUCK1 theoretical efficiency ...........................65

Fig. 18.

BUCK3 schematic ........................................... 66

Fig. 19.

Phase and gain margin simulation .................. 67

Fig. 20.

Transient response simulation .........................68

Fig. 21.

BUCK3 theoretical efficiency ...........................70

Fig. 22.

LDO1 block diagram ....................................... 70

Fig. 23.

Clock management block diagram .................. 72

Fig. 24.

Synchronization of two FS5502 ...................... 77

Fig. 25.

Two FS5502 synchronization timing

diagram ............................................................77

Fig. 26.

Synchronization of one FS5502 and one

external PMIC (PF82) ..................................... 78

Fig. 27.

FS5502 and one PF82 synchronization

timing diagram .................................................78

Fig. 28.

CRC encoder example ....................................80

Fig. 29.

Operating range .............................................. 82

Fig. 30.

FS5502 Application diagram ........................... 85

Fig. 31.

Fail-safe block diagram ...................................86

Fig. 32.

SVS principle ...................................................88

Fig. 33.

VDDIO monitoring principle .............................88

Fig. 34.

VMON1 monitoring principle ........................... 90

Fig. 35.

PGOOD pin implementation ............................92

Fig. 36.

RSTB pin implementation ............................... 93

Fig. 37.

Package outline for HVQFN56

(SOT684-23, Step-cut) .................................... 95

Fig. 38.

Package outline detail for HVQFN56

(SOT684-23, Step-cut) .................................... 96

Fig. 39.

Package outline for HVQFN56

(SOT684-23, Dimple) ...................................... 97

Fig. 40.

Package outline detail for HVQFN56

(SOT684-23, Dimple) ...................................... 98

Fig. 41.

Package outline notes for HVQFN56

(SOT684-23) ....................................................98

Fig. 42.

Solder mask pattern ......................................100

Fig. 43.

I/O pads and solderable areas ......................101

Fig. 44.

Solder paste stencil .......................................102

FS5502

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Product data sheet

Rev. 4 — 27 October 2021

111 / 113

FS5502 Datasheet(PDF) 111 Page - NXP Semiconductors

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