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FS5502 Datasheet(PDF) 113 Page - NXP Semiconductors |
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FS5502 Datasheet(HTML) 113 Page - NXP Semiconductors |
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113 / 113 page ![]() NXP Semiconductors FS5502 High voltage PMIC with multiple SMPS and LDO 27.3.1 Fault source and reaction ................................91 27.3.2 Fault error counter ...........................................92 27.4 PGOOD, RSTB ................................................92 27.4.1 PGOOD ............................................................92 27.4.2 RSTB ............................................................... 93 28 Package information .........................................94 29 Package outline .................................................95 29.1 Step-cut wettable flank .................................... 95 29.2 Dimple wettable flank ...................................... 97 29.3 Package comparison ....................................... 98 30 Layout and PCB guidelines ........................... 100 30.1 Landing pad information ................................ 100 30.2 Component selection .....................................102 30.3 VPRE ............................................................. 102 30.4 VBUCKx .........................................................104 31 EMC compliance ............................................. 104 32 References .......................................................105 33 Revision history .............................................. 106 34 Legal information ............................................108 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2021. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 27 October 2021 Document identifier: FS5502 |
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