TMS320F datasheet(342/389 Pages) TI

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Emulation Timing Calculations

C-7

Design Considerations for Using the XDS510 Emulator

C.5 Emulation Timing Calculations

The examples in this section help you calculate emulation timings in your sys-

tem. For actual target timing parameters, see the appropriate data sheet for

the device you are emulating.

The examples use the following assumptions:

tsu(TTMS)

Setup time, target TMS or TDI to TCK

high

10 ns

td(TTDO)

Delay time, target TDO from TCK low

15 ns

td(bufmax)

Delay time, target buffer maximum

10 ns

td(bufmin)

Delay time, target buffer minimum

1 ns

tbufskew

Skew time, target buffer between two de-

vices in the same package:

[td(bufmax) – td(bufmin)] × 0.15

1.35 ns

tTCKfactor

Duty cycle, assume a 40/60% duty cycle

clock

0.4

(40%)

Also, the examples use the following values from Table C–2 on page C-6:

td(TMSmax)

Delay time, emulator TMS or TDI from

TCK_RET low, maximum

20 ns

tsu(TDOmin)

Setup time, TDO to emulator TCK_RET

high, minimum

3 ns

There are two key timing paths to consider in the emulation design:

- TheTCK_RET-to-TMSorTDIpath,calledtpd(TCK_RET-TMS/TDI)(propaga-

tion delay time)

- The TCK_RET-to-TDO path, called tpd(TCK_RET-TDO)

In the examples, the worst-case path delay is calculated to determine the

maximum system test clock frequency.

TMS320F Datasheet(PDF) 342 Page - Texas Instruments

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