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TMS320F Datasheet(PDF) 339 Page - Texas Instruments |
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TMS320F Datasheet(HTML) 339 Page - Texas Instruments |
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339 / 389 page  Bus Protocol C-4 C.2 Bus Protocol The IEEE 1149.1 specification covers the requirements for the test access port (TAP) bus slave devices and provides certain rules, summarized as follows: - The TMS and TDI inputs are sampled on the rising edge of the TCK signal of the device. - The TDO output is clocked from the falling edge of the TCK signal of the device. When these devices are daisy-chained together, the TDO of one device has approximately a half TCK cycle setup time before the next device’s TDI signal. This timing scheme minimizes race conditions that would occur if both TDO and TDI were timed from the same TCK edge. The penalty for this timing scheme is a reduced TCK frequency. The IEEE 1149.1 specification does not provide rules for bus master (emula- tor) devices. Instead, it states that the device expects a bus master to provide bus slave compatible timings. The XDS510 provides timings that meet the bus slave rules. |
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