TMS320F datasheet(373/389 Pages) TI

373 / 389 page

Glossary

D-13

Glossary

PSLWS:

Lower program-space wait-state bits. A value in the wait-state

generator control register (WSGR) that determines the number of wait

states applied to reads from and writes to off-chip lower program space

(addresses 0000h–7FFFh). See also

PSUWS.

PSUWS:

Upper program-space wait-state bits. A value in the wait-state

generator control register (WSGR) that determines the number of wait

states applied to reads from and writes to off-chip upper program space

(addresses 8000h–FFFFh). See also

PSLWS.

RD:

Read select pin. The ’C24x asserts RD to request a read from external

program, data, or I/O space. RD can be connected directly to the output

enable pin of an external device.

READY:

External device ready pin. Used to create wait states externally.

When this pin is driven low, the ’C24x waits one CPU cycle and then tests

READY again. After READY is driven low, the ’C24x does not continue

processing until READY is driven high.

repeat counter (RPTC):

A 16-bit register that counts the number of times

a single instruction is repeated. RPTC is loaded by an RPT instruction.

reset:

A way to bring the processor to a known state by setting the registers

and control bits to predetermined values and signaling execution to start

at address 0000h.

reset pin (RS):

A pin that causes a reset.

reset vector:

The interrupt vector for reset.

return address:

The address of the instruction to be executed when the

CPU returns from a subroutine or interrupt service routine.

RPTC:

See

repeat counter (RPTC).

RS:

Reset pin. When driven low, causes a reset on any ’C24x device.

R/W:

Read/write pin. Indicates the direction of transfer between the ’C24x

and external program, data, or I/O space.

SARAM:

Single-access RAM. RAM that can be accessed (read from or writ-

ten to) once in a single CPU cycle.

TMS320F Datasheet(PDF) 373 Page - Texas Instruments

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