TMS320F datasheet(369/389 Pages) TI

369 / 389 page

Glossary

D-9

Glossary

latch phase:

The phase of a CPU cycle during which internal values are held

constant. See also

logic phase; CLKOUT1.

local data space:

The portion of data-memory addresses that are not allo-

cated as global by the global memory allocation register (GREG). If none

of the data-memory addresses are allocated for global use, all of data

space is local. See also

global data space.

logic phase:

The phase of a CPU cycle during which internal values are

changed. See also

latch phase; CLKOUT1.

long-immediate value:

A 16-bit constant given as an operand of an

instruction that is using immediate addressing.

LSB:

Least significant bit. The lowest order bit in a word. When used in plural

form (LSBs), refers to a specified number of low-order bits, beginning

with the lowest order bit and counting to the left. For example, the four

LSBs of a 16-bit value are bits 0 through 3. See also

MSB.

machine cycle:

See

CPU cycle.

maskable interrupt:

A hardware interrupt that can be enabled or disabled

through software. See also

nonmaskable interrupt.

master clock output signal:

See

CLKOUT1.

master phase:

See

logic phase.

memory-mapped register:

One of the on-chip registers mapped to

addresses in data memory. See also

I/O-mapped register.

microcomputer mode:

A mode in which the on-chip ROM or flash memory

is enabled. This mode is selected with the MP/MC pin. See also

MP/MC

pin; microprocessor mode.

microprocessor mode:

A mode in which the on-chip ROM or flash memory

is disabled. This mode is selected with the MP/MC pin. See also

MP/MC

pin; microcomputer mode.

microstack (MSTACK):

A register used for temporary storage of the

program counter (PC) value when an instruction needs to use the PC to

address a second operand.

TMS320F Datasheet(PDF) 369 Page - Texas Instruments

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