TMS320F datasheet(366/389 Pages) TI

366 / 389 page

Glossary

D-6

execute phase:

The fourth phase of the pipeline; the phase in which the

instruction is executed. See also

pipeline; instruction-fetch phase;

instruction-decode phase; operand-fetch phase.

external interrupt:

A hardware interrupt triggered by an external event

sending an input through an interrupt pin.

FIFO buffer:

First-in, first-out buffer. A portion of memory in which data is

stored and then retrieved in the same order in which it was stored. The

synchronous serial port has two four-word-deep FIFO buffers: one for its

transmit operation and one for its receive operation.

flash memory:

Electronically erasable and programmable, nonvolatile

(read-only) memory.

general-purpose input/output pins:

Pins that can be used to accept input

signals or send output signals. These pins are the input pin BIO, the out-

put pin XF, and the GPIO pins.

global data space:

One of the four ’C24x address spaces. The global data

space can be used to share data with other processors within a system

and can serve as additional data space. See also

local data space.

GREG:

Global memory allocation register.

A memory-mapped register

used for specifying the size of the global data memory. Addresses not

allocated by the GREG for global data memory are available for local

data memory.

hardware interrupt:

An interrupt triggered through physical connections

with on-chip peripherals or external devices.

TMS320F Datasheet(PDF) 366 Page - Texas Instruments