| Electronic Components Datasheet Search |
|
TMS320F Datasheet(PDF) 370 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
TMS320F Datasheet(HTML) 370 Page - Texas Instruments |
|
370 / 389 page ![]() Glossary D-10 MIPS: Million instructions per second. MP/MC pin: A pin that indicates whether the processor is operating in micro- processor mode or microcomputer mode. MP/MC high selects micropro- cessor mode; MP/MC low selects microcomputer mode. MSB: Most significant bit. The highest order bit in a word. When used in plural form (MSBs), refers to a specified number of high-order bits, begin- ning with the highest order bit and counting to the right. For example, the eight MSBs of a 16-bit value are bits 15 through 8. See also LSB. MSTACK: See microstack. multiplier: A part of the CPU that performs 16-bit × 16-bit multiplication and generates a 32-bit product. The multiplier operates using either signed or unsigned 2s-complement arithmetic. N next AR: See next auxiliary register. next auxiliary register: The register that is pointed to by the auxiliary regis- ter pointer (ARP) when an instruction that modifies ARP is finished executing. See also auxiliary register; current auxiliary register. NMI: A hardware interrupt that uses the same logic as the maskable inter- rupts but cannot be masked. It is often used as a soft reset. See also maskable interrupt; nonmaskable interrupt. nonmaskable interrupt: An interrupt that can be neither masked by the interrupt mask register (IMR) nor disabled by the INTM bit of status register ST0. NPAR: Next program address register. Part of the program-address genera- tion logic. This register provides the address of the next instruction to the program counter (PC), the program address register (PAR), the micro stack (MSTACK), or the stack. O operand: A value to be used or manipulated by an instruction; specified in the instruction. operand-fetch phase: The third phase of the pipeline; the phase in which an operand or operands are fetched from memory. See also pipeline; instruction-fetch phase; instruction-decode phase; instruction-execute phase. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |