TMS320F datasheet(367/389 Pages) TI

367 / 389 page

Glossary

D-7

Glossary

immediate addressing:

One of the methods for obtaining data values used

by an instruction; the data value is a constant embedded directly into the

instruction word; data memory is not accessed.

immediate operand/immediate value:

A constant given as an operand in

an instruction that is using immediate addressing.

IMR:

See

interrupt mask register (IMR).

indirect addressing:

One of the methods for obtaining data values used by

an instruction. When an instruction uses indirect addressing, data

memory is addressed by the current auxiliary register. See also

direct

addressing.

input clock signal:

See

CLKIN.

input shifter:

A 16- to 32-bit left barrel shifter that shifts incoming 16-bit data

from 0 to 16 positions left relative to the 32-bit output.

instruction-decode phase:

The second phase of the pipeline; the phase in

which the instruction is decoded. See also

pipeline; instruction-fetch

phase; operand-fetch phase; instruction-execute phase.

instruction-execute phase:

The fourth phase of the pipeline; the phase in

which the instruction is executed. See also

pipeline; instruction-fetch

phase; instruction-decode phase; operand-fetch phase.

instruction-fetch phase:

The first phase of the pipeline; the phase in which

the instruction is fetched from program-memory. See also

pipeline;

instruction-decode phase; operand-fetch phase; instruction-execute

phase.

instruction register (IR):

A 16-bit register that contains the instruction

being executed.

instruction word:

A 16-bit value representing all or half of an instruction. An

instruction that is fully represented by 16 bits uses one instruction word.

An instruction that must be represented by 32 bits uses two instruction

words (the second word is a constant).

internal interrupt:

A hardware interrupt caused by an on-chip peripheral.

interrupt:

A signal sent to the CPU that (when not masked or disabled)

forces the CPU into a subroutine called an interrupt service routine (ISR).

This signal can be triggered by an external device, an on-chip peripheral,

or an instruction (INTR, NMI, or TRAP).

TMS320F Datasheet(PDF) 367 Page - Texas Instruments

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