TMS320F datasheet(368/389 Pages) TI

368 / 389 page

Glossary

D-8

interrupt acknowledge signal (IACK):

A signal that indicates an interrupt

has been received and that the program counter is fetching the interrupt

vector that will force the processor into the appropriate interrupt service

routine.

interrupt flag register (IFR):

A 16-bit memory-mapped register that indi-

cates pending interrupts. Read the IFR to identify pending interrupts and

write to the IFR to clear selected interrupts. Writing a 1 to any IFR flag

bit clears that bit to 0.

interrupt latency:

The delay between the time an interrupt request is made

and the time it is serviced.

interrupt mask register (IMR):

A 16-bit memory-mapped register used to

mask external and internal interrupts. Writing a 1 to any IMR bit position

enables the corresponding interrupt (when INTM = 0).

interrupt mode bit (INTM):

Bit 9 in status register ST0; either enables all

maskable interrupts that are not masked by the IMR or disables all mask-

able interrupts.

interrupt service routine (ISR):

A module of code that is executed in

response to a hardware or software interrupt.

interrupt trap:

See

interrupt service routine (ISR).

interrupt vector:

A branch instruction that leads the CPU to an interrupt

service routine (ISR).

interrupt vector location:

An address in program memory where an inter-

rupt vector resides. When an interrupt is acknowledged, the CPU

branches to the interrupt vector location and fetches the interrupt vector.

INTM bit:

See

interrupt mode bit (INTM).

I/O-mapped register:

One of the on-chip registers mapped to addresses in

I/O (input/output) space. These registers, which include the registers for

the on-chip peripherals, must be accessed with the IN and OUT instruc-

tions. See also

memory-mapped register.

IR:

See

instruction register (IR).

IS:

I/O space select pin. The ’C24x asserts IS to indicate an access to exter-

nal I/O space.

ISR:

See

interrupt service routine (ISR).

ISWS:

I/O-space wait-state bit(s). A value in the wait-state generator control

reads from and writes to off-chip I/O space.

TMS320F Datasheet(PDF) 368 Page - Texas Instruments

TMS320F Datasheet(HTML) 368 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL