TMS320F datasheet(371/389 Pages) TI

371 / 389 page

Glossary

D-11

Glossary

output shifter:

32- to 16-bit barrel left shifter. Shifts the 32-bit accumulator

output from 0 to 7 bits left for quantization management, and outputs

either the 16-bit high or low half of the shifted 32-bit data to the data write

bus (DWEB).

OV bit:

Overflow flag bit. Bit 12 of status register ST0; indicates whether the

result of an arithmetic operation has exceeded the capacity of the

accumulator.

overflow (in a register):

A condition in which the result of an arithmetic

operation exceeds the capacity of the register used to hold that result.

overflow mode:

The mode in which an overflow in the accumulator causes

the accumulator to be loaded with a preset value. If the overflow is in the

positive direction, the accumulator is loaded with its most positive

number. If the overflow is in the negative direction, the accumulator is

filled with its most negative number.

OVM bit:

Overflow mode bit. Bit 11 of status register ST0; enables or

disables overflow mode. See also

overflow mode.

PAB:

See

program address bus (PAB).

PAR:

Program address register. A register that holds the address currently

being driven on the program address bus for as many cycles as it takes

to complete all memory operations scheduled for the current machine

cycle.

PC:

See

program counter (PC).

PCB:

Printed circuit board.

pending interrupt:

A maskable interrupt that has been successfully

requested but is awaiting acknowledgement by the CPU.

pipeline:

A method of executing instructions in an assembly line fashion.

The ’C24x pipeline has four independent phases. During a given CPU

cycle, four different instructions can be active, each at a different stage

of completion. See also

instruction-fetch phase; instruction-decode

phase; operand-fetch phase; instruction-execute phase.

PLL:

Phase lock loop circuit.

PM bits:

See

product shift mode bits (PM).

TMS320F Datasheet(PDF) 371 Page - Texas Instruments

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