TMS320F datasheet(375/389 Pages) TI

375 / 389 page

Glossary

D-15

Glossary

TC bit:

Test/control flag bit.

Bit 11 of status register ST1; stores the results

of test operations done in the central arithmetic logic unit (CALU) or the

auxiliary register arithmetic unit (ARAU). The TC bit can be tested by

conditional instructions.

temporary register (TREG):

A 16-bit register that holds one of the oper-

ands for a multiply operation; the dynamic shift count for the LACT,

ADDT, and SUBT instructions; or the dynamic bit position for the BITT

instruction.

TOS:

Top of stack. Top level of the 8-level last-in, first-out hardware stack.

TREG:

See

temporary register (TREG).

TTL:

Transistor-to-transistor logic.

vector:

See

interrupt vector.

vector location:

See

interrupt vector location.

wait state:

A CLKOUT1 cycle during which the CPU waits when reading

from or writing to slower external memory.

wait-state generator:

An on-chip peripheral that generates a limited

number of wait states for a given off-chip memory space (program, data,

or I/O). Wait states are set in the wait-state generator control register

(WSGR).

WE:

Write enable pin. The ’C24x asserts WE to request a write to external

program, data, or I/O space.

WSGR:

Wait-state generator control register. This register, which is mapped

to I/O memory, controls the wait-state generator.

XF bit:

XF-pin status bit. Bit 4 of status register ST1 that is used to read or

change the logic level on the XF pin.

TMS320F Datasheet(PDF) 375 Page - Texas Instruments

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