TMS320F datasheet(365/389 Pages) TI

365 / 389 page

Glossary

D-5

Glossary

data page pointer (DP):

A 9-bit field in status register ST0 that specifies

which of the 512 data pages is currently selected for direct address

generation. When an instruction uses direct addressing to access a data-

memory value, the DP provides the nine MSBs of the data-memory

address, and the instruction provides the seven LSBs.

data-read address bus (DRAB):

A 16-bit internal bus that carries the

address for each read from data memory.

data read bus (DRDB):

A 16-bit internal bus that carries data from data

memory to the CALU and the ARAU.

data-write address bus (DWAB):

A 16-bit internal bus that carries the

address for each write to data memory.

data write bus (DWEB):

A 16-bit internal bus that carries data to both

program memory and data memory.

decode phase:

The phase of the pipeline in which the instruction is

decoded. See also

pipeline; instruction-fetch phase; operand-fetch

phase; instruction-execute phase.

direct addressing:

One of the methods used by an instruction to address

data-memory. In direct addressing, the data-page pointer (DP) holds the

nine MSBs of the address (the current data page), and the instruction

word provides the seven LSBs of the address (the offset). See also

indirect addressing.

DP:

See

data page pointer (DP).

DRAB:

See

data-read address bus (DRAB).

DRDB:

See

data read bus (DRDB).

DS:

Data memory select pin. The ’C24x asserts DS to indicate an access to

external data memory (local or global).

DSWS:

Data-space wait-state bit(s). A value in the wait-state generator

control register (WSGR) that determines the number of wait states

applied to reads from and writes to off-chip data space.

dual-access RAM:

See

DARAM.

dummy cycle:

A CPU cycle in which the CPU intentionally reloads the

program counter with the same address.

DWAB:

See

data-write address bus (DWAB).

DWEB:

See

data write bus (DWEB).

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