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TMS320F Datasheet(PDF) 380 Page - Texas Instruments

Part # TMS320F
Description  CPU and Instruction Set
PDF  389 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320F Datasheet(HTML) 380 Page - Texas Instruments

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Index
Index-3
B
B instruction
7-38
BACC instruction
7-39
BANZ instruction
7-40
BCND instruction
7-42
BIT instruction
7-44
bit-reversed indexed addressing
6-10, D-2
BITT instruction
7-46
BLDD instruction
7-48
block diagrams
ARAU and related logic
4-12
arithmetic logic section of CPU
4-8
auxiliary registers (AR0–AR7) and ARAU
4-12
CPU (selected sections)
4-2
input scaling section of CPU
4-3
multiplication section of CPU
4-5
program-address generation
5-2
block move instructions
block move from data memory to data memory
(BLDD)
7-48
block move from program memory to data
memory (BLPD)
7-53
BLPD instruction
7-53
Boolean logic instructions
AND
7-33
CMPL (complement/NOT)
7-63
OR
7-128
XOR (exclusive OR)
7-192
BR signal
4-18
branch instructions
branch conditionally (BCND)
7-42
branch if current auxiliary register not zero
(BANZ)
7-40
branch to location specified by accumulator
(BACC)
7-39
branch to NMI interrupt vector location
(NMI)
7-123
branch to specified interrupt vector location
(INTR)
7-70
branch to TRAP interrupt vector location
(TRAP)
7-191
branch unconditionally (B)
7-38
call subroutine at location specified by
accumulator (CALA)
7-57
call subroutine conditionally (CC)
7-59
call subroutine unconditionally (CALL)
7-58
conditional, overview
5-11
branch instructions
(continued)
return conditionally from subroutine
(RETC)
7-142
return unconditionally from subroutine
(RET)
7-141
unconditional, overview
5-8
branches, calls, and returns
5-8
buffered signals, JTAG
C-10
buffering
C-10
bus devices
C-4
bus protocol in emulator system
C-4
buses
data read bus (DRDB)
2-4
data write bus (DWEB)
2-4
data-read address bus (DRAB)
2-4
data-write address bus (DWAB)
2-4
program address bus (PAB)
2-4
used in program-memory address
generation
5-3
program read bus (PRDB)
2-4
C
’C24x, features, emulation
2-10
C (carry bit)
affected during SFL and SFR instructions
7-156
to 7-158
definition
4-16
involved in accumulator events
4-10
used during ROL and ROR instructions
7-143
to 7-145
cable, target system to emulator
C-1 to C-25
cable pod
C-5, C-6
CALA instruction
7-57
CALL instruction
7-58
call instructions
call subroutine at location specified by
accumulator (CALA)
7-57
call subroutine conditionally (CC)
7-59
call subroutine unconditionally (CALL)
7-58
conditional, overview
5-12
unconditional, overview
5-8
CALU (central arithmetic logic unit)
definition
D-3
description
4-9
CALU (central atithmetic logic unit)
2-8
carry bit (C)
affected during SFL and SFR instructions
7-156
to 7-158



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