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TMS320F Datasheet(PDF) 384 Page - Texas Instruments

Part # TMS320F
Description  CPU and Instruction Set
PDF  389 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320F Datasheet(HTML) 384 Page - Texas Instruments

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Index
Index-7
INT31 interrupt, vector location
5-16
INT8 interrupt, vector location
5-15 to 5-17
INT9 interrupt, vector location
5-16
internal memory
dual-access RAM
2-5
organization
2-5
interrupt
definitions
D-7
interrupt mode bit (INTM)
4-16
maskable interrupt, interrupt mode bit
(INTM)
4-16
interrupt flag register (IFR)
3-7, 5-17 to 5-20
interrupt latency, definition
D-8
interrupt mask register (IMR)
3-7, 5-19 to 5-20
interrupt mode bit (INTM)
4-16
interrupt service routines (ISRs), definition
D-8
interrupts
5-15
hardware, priorities, ’C24x
5-15, 5-16
IMR register
5-19
interrupt mask register
5-19
masking, interrupt mask register (IMR)
5-19 to
5-20
pending, interrupt flag register (IFR)
5-17 to
5-20
INTM (interrupt mode bit)
4-16
INTR instruction
7-70
introduction
accumulator
2-8
ARAU (auxiliary register arithmetic unit)
2-9
auxiliary registers
2-9
CALU (central arithmetic logic unit)
2-8
multiplier
2-9
registers
2-9
scaling shifters
2-8
shifters
2-8
IR (instruction register), definition
D-7
IS signal
4-18
ISR (interrupt service routine), definition
D-8
J
JTAG
C-16
JTAG emulator
buffered signals
C-10
connection to target system
C-1 to C-25
no signal buffering
C-10
L
LACC instruction
7-71
LACL instruction
7-74
LACT instruction
7-77
LAR instruction
7-79
latch phase of CPU cycle
D-9
LDP instruction
7-82
local data memory
3-6
logic instructions
AND
7-33
CMPL (complement/NOT)
7-63
OR
7-128
XOR (exclusive OR)
7-192
logic phase of CPU cycle
D-9
long immediate addressing
6-2
LPH instruction
7-84
LR signal
4-18
LST instruction
7-86
LT instruction
7-90
LTA instruction
7-92
LTD instruction
7-94
LTP instruction
7-97
LTS instruction
7-99
M
MAC instruction
7-101
MACD instruction
7-105
MAR instruction
7-110
memory
address map, data page 0
3-7
buses
3-2
configuration
data
3-8
global data memory
3-9 to 3-10
off-chip data memory
3-8
on-chip data memory
3-8
data page pointer (DP)
4-16
dual-access RAM
2-5
external memory interface timings
4-18
global data memory
3-9 to 3-10
address generation
3-11
I/O space
3-11
local data
3-6 to 3-8
on-chip, advantages
3-2
organization
2-5, 3-2



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