TMS320F datasheet(385/389 Pages) TI

385 / 389 page

Index

Index-8

memory

(continued)

program

3-4 to 3-5

program memory

address generation logic

5-2

address sources

5-3

segments

3-2

total address range

3-1

memory instructions

block move from data memory to data memory

(BLDD)

7-48

block move from program memory to data

memory (BLPD)

7-53

move data after add PREG to accumulator, load

TREG, and multiply (MACD)

7-105

move data to next higher address in data

memory (DMOV)

7-65

move data, load TREG, and add PREG to

accumulator (LTD)

7-94

store long immediate value to data memory

(SPLK)

7-164

table read (TBLR)

7-185

table write (TBLW)

7-188

transfer data from data memory to I/O space

(OUT)

7-131

transfer data from I/O space to data memory

(IN)

7-68

transfer word from data memory to program

memory (TBLW)

7-188

transfer word from program memory to data

memory (TBLR)

7-185

memory maps for ’C24x controllers

3-3

microstack (MSTACK)

5-3, 5-6

MP/MC pin

3-5

MPY instruction

7-112

MPYA instruction

7-115

MPYS instruction

7-117

MPYU instruction

7-119

MSTACK (microstack)

5-3, 5-6

multiplication section of CPU

4-5

multiplier

2-9

description

4-5

multiply instructions

multiply (include load to TREG) and accumulate

previous product (MAC)

7-101

multiply (include load to TREG), accumulate

previous product, and move data

(MACD)

7-105

multiply (MPY)

7-112

multiply instructions

(continued)

multiply and accumulate previous product

(MPYA)

7-115

multiply and subtract previous product

(MPYS)

7-117

multiply unsigned (MPYU)

7-119

square specified value after accumulating

previous product (SQRA)

7-167

square specified value after subtracting previous

product from accumulator (SQRS)

7-169

NEG instruction

7-121

next auxiliary register

6-11

next program address register (NPAR)

definition

D-10

shown in figure

5-2

NMI instruction

7-123

vector location

5-16

NMI interrupt, vector location

5-16

NOP instruction

7-124

NORM instruction

7-125

NPAR (next program address register)

definition

D-10

shown in figure

5-2

off-chip memory, configuration, data

3-8

on-chip memory

advantages

3-2

configuration

3-8

on-chip RAM, dual-access

2-5

on-chip ROM

B-1

opcode format

direct addressing

6-5

immediate addressing

6-2

indirect addressing

6-12

OR instruction

7-128

OUT instruction

7-131

output modes

external count

C-20

signal event

C-20

output shifter

2-8, 4-11

OV (overflow flag bit)

4-16

TMS320F Datasheet(PDF) 385 Page - Texas Instruments

TMS320F Datasheet(HTML) 385 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL