TMS320F datasheet(388/389 Pages) TI

388 / 389 page

Index

Index-11

SFL instruction

7-156

SFR instruction

7-157

shifters

2-8

input shifter

4-3

output shifter

4-11

product shifter

4-6

product shift modes

4-7

short immediate addressing

6-2

signal descriptions, 14-pin header

C-3

signals

buffered

C-10

buffering for emulator connections

C-10 to C-13

description, 14-pin header

C-3

timing

C-6

sign-extension mode bit (SXM)

definition

4-17

effect on CALU (central arithmetic logic

unit)

4-9

effect on input shifter

4-4

single-access RAM (SARAM), definition

D-13

slave devices

C-4

SPAC instruction

7-159

SPH instruction

7-160

SPL instruction

7-162

SPLK instruction

7-164

SPM instruction

7-166

SQRA instruction

7-167

SQRS instruction

7-169

SST instruction

7-171

stack

5-3, 5-4

pop top of stack to data memory (POPD

instruction)

7-136

pop top of stack to low accumulator bits (POP

instruction)

7-134

push data memory value onto stack (PSHD

instruction)

7-138

push low accumulator bits onto stack (PUSH

instruction)

7-140

status registers ST0 and ST1

bits

4-15

clear control bit (CLRC instruction)

7-61

introduction

4-15

load (LST instruction)

7-86

load data page pointer (LDP instruction)

7-82

modify auxiliary register pointer (MAR

instruction)

7-110

status registers ST0 and ST1

(continued)

set control bit (SETC instruction)

7-154

set product shift mode (SPM instruction)

7-166

store (SST instruction)

7-171

stop bits (1 or 2)

5-18

STRB signal

4-18

SUB instruction

7-173

SUBB instruction

7-177

SUBC instruction

7-179

SUBS instruction

7-181

SUBT instruction

7-183

SXM (sign-extension mode bit)

definition

4-17

effect on CALU (central arithmetic logic

unit)

4-9

effect on input shifter

4-4

target cable

C-14

target system, connection to emulator

C-1 to C-25

target system emulator connector, designing

C-2

target-system clock

C-12

TBLR instruction

7-185

TBLW instruction

7-188

TC (test/control flag bit)

4-17

response to accumulator event

4-10

response to auxiliary register compare

4-14

TCK signal

C-2 to C-7, C-13, C-17, C-18, C-25

TDI signal

C-2 to C-8, C-13, C-18

TDO signal

C-4, C-5, C-8, C-19, C-25

temporary register (TREG)

4-6

test bus controller

C-22, C-24

test clock

C-12

diagram

C-12

test/control flag bit (TC)

4-17

response to accumulator event

4-10

response to auxiliary register compare

4-14

timing, external memory interface

4-18

timing calculations

C-7 to C-9, C-18 to C-26

TMS signal

C-2 to C-8, C-13, C-17 to C-19, C-25

TMS/TDI inputs

C-4

TMS320 family

1-2 to 1-6

advantages

1-2

development

1-2

history

1-2

overview

1-2

TMS320F Datasheet(PDF) 388 Page - Texas Instruments

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