TMS320F datasheet(387/389 Pages) TI

387 / 389 page

Index

Index-10

program control features

(continued)

stack

5-4

status registers ST0 and ST1

4-15

bits

4-15

program counter (PC)

5-3, 5-4

description

5-4

shown in figure

5-2

program memory

3-2, 3-4

address generation logic

5-2

microstack (MSTACK)

5-6

program counter (PC)

5-4

stack

5-4

address sources

5-3

configuration

3-5

program memory maps for ’C24x

3-4

program read bus (PRDB)

2-4

program-address generation (diagram)

5-2

protocol, bus, in emulator system

C-4

PS signal

4-18

PSHD

5-5

PSHD instruction

7-138

PUSH

5-5

PUSH instruction

7-140

push operation (diagram)

5-5

R/W pin

4-19

R/W signal

4-18

RAM, dual-access on-chip

2-5

RD signal

4-18

read/write timings

4-18

registers

auxiliary registers

2-9

current auxiliary register

6-12

auxiliary registers (AR0–AR7)

current auxiliary register

6-9

next auxiliary register

6-11

interrupt flag register (IFR)

5-17 to 5-20

interrupt mask register (IMR)

5-19 to 5-20

mapped to data page 0

3-7

status registers ST0 and ST1

4-15

repeat (RPT) instruction

description

7-145

introduction

5-14

repeat counter (RPTC)

5-3, 5-14

repeating a single instruction

5-14

reset

priority

5-15

vector location

5-15

RET instruction

7-141

RETC instruction

7-142

return instructions

conditional, overview

5-12

return conditionally from subroutine

(RETC)

7-142

return unconditionally from subroutine

(RET)

7-141

unconditional, overview

5-9

ROL instruction

7-143

ROM, customized

B-1 to B-4

ROM codes, submitting to Texas Instruments

B-1

to B-4

ROR instruction

7-144

RPT instruction

7-145

RPTC (repeat counter)

5-3, 5-14

priority

5-15

vector location

5-15

run/stop operation

C-10

RUNB, debugger command

C-20 to C-24

RUNB_ENABLE, input

C-22

SACH instruction

7-147

SACL instruction

7-149

SAR instruction

7-151

SARAM (single-access RAM), definition

D-13

SBRK instruction

7-153

scaling shifters

2-8

input shifter

4-3

output shifter

4-11

product shifter

4-6

product shift modes

4-7

scan path linkers

C-16

secondary JTAG scan chain to an SPL

C-17

suggested timings

C-22

usage

C-16

scan paths, TBC emulation connections for JTAG

scan paths

C-25

serial-scan emulation

2-10

SETC instruction

7-154

TMS320F Datasheet(PDF) 387 Page - Texas Instruments

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